Patent Application
20080242108
1. Field of the Invention
The invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a metal electrode capable of eliminating surface oxidation due to the ambient environment.
2. Description of the Related Art
A metal oxide semiconductor field effect transistor (MOSFET) comprises a gate structure disposed between source and drain regions formed in a substrate. The gate structure typically comprises a gate electrode and a gate dielectric. The gate electrode is disposed over the gate dielectric to control a flow of charge carriers in a channel region formed between the drain and source regions under the gate dielectric. To reduce equivalent oxide thickness (EOT) at the 65 nm generation technology node and beyond, the gate dielectric may be formed from a material having a dielectric constant greater than 4. Materials for forming the gate electrode may comprise metal. Such dielectric materials are referred to as high-k materials in this specification. To maintain work function and reduce difficulty in post gate stack integration, a polysilicon layer is disposed on the metal to form a gate stack.
Typically, the metal layer of the gate stack is formed by physical vapor deposition (PVD) and the polysilicon layer of the gate stack is formed by chemical vapor deposition (CVD). In conventional MOSFET fabrication, the substrate must pass between various tools. Transporting the substrate between tools requires the removal of the substrate from the vacuum environment of one tool for transfer at ambient pressures to the vacuum environment of a second tool. In the ambient environment, the substrates are exposed to mechanical and chemical contaminants, such as particles, moisture and others, that may damage the gate electrode being fabricated and possibly form an undesired layer, such as, a native oxide layer.
As shown in
Thus, a method for fabricating a semiconductor device, capable of reducing EOT and enhancing device performance by eliminating exposure of the substrate to the ambient environment, is desirable.
The invention provides a method for fabricating a semiconductor device capable of reducing EOT and increasing device performance by preventing the formation of metal oxide resulting from exposure to the ambient.
An exemplary embodiment of a method for fabricating a semiconductor device, comprises: providing a semiconductor substrate; providing a first chamber and a second chamber connected by a pressure differential unit; depositing a metallic film over the substrate in the first chamber; transferring the substrate to the second chamber via the pressure differential unit without exposing the substrate to the ambient environment and depositing a silicon-containing film on the metallic film in the second chamber.
In one embodiment, the first chamber may be a CVD, PVD, LPCVD, PECVD or ALCVD chamber, and the second chamber may be a LPCVD or PECVD chamber. The first chamber and the second chamber can be different chambers of a single cluster tool system or chambers of different cluster tool systems. No metal oxide is formed between the metallic film and the silicon-containing film.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
The invention provides a method for fabricating a semiconductor device by in-situ deposition of a metallic film and a silicon-containing film to avoid formation of metal oxide. In one embodiment, the metallic film and the silicon-containing film are deposited in different chambers of a single cluster tool system. In another embodiment, the metallic film and the silicon-containing film are deposited in different chambers of two cluster tool systems. The metallic film can be deposited by a chemical vapor deposition (CVD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALCVD). The silicon-containing film can be deposited by a LPCVD or PECVD.
The first cluster tool system 210 comprises a platform 203 and a chamber 209. The vacuum environment of the platform 203 is about 0.1˜20 torr for CVD process and 10E-6˜10E-8 torr for PVD process. Although in the figure, the first cluster tool system 210 only comprises one chamber, those skilled in the art will recognize the cluster tool system 210 can comprise more than one chamber. The chamber 209 can be a CVD, PVD, LPCVD, PECVD or ALCVD chamber for deposition of the metallic film, wherein a PVD chamber is preferred. The pressure of the chamber 209 is about 0.01˜20 mtorr for a PVD chamber and 0.1˜500 torr for a CVD chamber.
The second cluster tool system 220 comprises a platform 205 and a chamber 211. The vacuum environment of the platform 205 is about 0.1˜20 torr. Those skilled in the art will recognize that the cluster tool system 220 may comprise more than one chamber. The chamber 211 can be a LPCVD or PECVD chamber for deposition of the silicon-containing film, wherein a LPCVD chamber is preferred. The pressure of the chamber 211 is about 1˜400 torr.
The load/unload unit 201 loads a wafer on or unloads a wafer from, cluster tool system 210. The pressure of the load/unload unit 201 is required to facilitate passage of the substrate between the vacuum environment of the platforms 203 and the ambient environment outside of the load/unload unit 201. The platforms 203 and 205 transfer the wafer into or out of the chambers. In equipment configuration 200, the pressure differential unit 207 connects the chambers 209 and 211. Thus, the wafer is transferred from the chamber 209 to the chamber 211 via the pressure differential unit without exposing the wafer to the ambient environment. Additionally, the pressure differential unit 207 can comprise a load lock chamber (not shown).
The chamber 305 can be a CVD, PVD, LPCVD, PECVD or ALCVD chamber for deposition of the metallic film, wherein a PVD, CVD or ALD chamber are preferred. The pressure of the chamber 305 is about 0.01˜20 mtorr for a PVD chamber and 0.1˜500 torr for a CVD chamber. The chamber 307 can be a CVD or PECVD chamber for deposition of the silicon-containing film, wherein a CVD chamber is preferred. The pressure of the chamber 307 is about 1˜400 torr. Although in the figure, only the cluster tool system 310 only comprises two chambers, those skilled in the art will recognize the cluster tool system 310 can comprise more than two chambers.
The load/unload unit 301 loads a wafer to, or unloads a wafer from, the cluster tool system 310. The pressure of the load/unload unit 301 facilitates passage of the substrate between the vacuum environment of the pressure differential unit 303 and the substantially ambient environment of outside of the load/unload unit 301. In the equipment configuration 300, the pressure differential unit 303 connects the chamber 305 and 307, thus, the wafer is transferred from the chamber 305 to the chamber 307 via the pressure differential unit without exposing the wafer to the ambient environment. The pressure differential unit 303 can also be a platform for transferring the wafer into or out of the chambers and can comprise a load lock chamber (not shown).
In one embodiment, the gate stack can be formed in the equipment configuration 200 of two cluster tool systems as shown in
In another embodiment, the gate stack can be formed in the equipment configuration 300 of single cluster tool system as shown in
The metallic film 44 and the silicon-containing film 46 can be patterned into a gate electrode of a transistor subsequent to deposition over the substrate. Because the inventive method utilizes an equipment configuration of chambers connected by the pressure differential unit to deposit the metallic film and the silicon-containing film without exposing the substrate to the ambient environment, the formation of metal oxide between the metallic film and the silicon-containing film is avoided. The method can reduce EOT about 2 to 6 Å and reduce leakage current of very shallow source/drain junctions required by 65 nm and newer technologies to enhance the performance of semiconductor devices.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
