Method for fabricating semiconductor device

Abstract

According to the present invention, a method for fabricating a semiconductor device includes: providing a semiconductor substrate; forming a STI region on the semiconductor substrate; forming a channel region on the semiconductor substrate; implanting impurities into the STI region; and performing a thermal treatment to diffuse impurities to a side of the channel region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view illustrating a conventional LOCOS region of a semiconductor device.

FIG. 2 is a cross sectional view illustrating a conventional semiconductor element.

FIGS. 3A-3G are cross-sectional views illustrating fabrication steps of a semiconductor device according to a first preferred embodiment of the present invention.

FIG. 4 is a graph showing an effect and advantage of the first preferred embodiment of the present invention.

FIGS. 5A-5H are cross-sectional views illustrating fabrication steps of a semiconductor device according to a second preferred embodiment of the present invention.

DETAILED DISCLOSURE OF THE INVENTION

In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These preferred embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other preferred embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and scope of the present inventions is defined only by the appended claims.

FIGS. 3A-3G are cross-sectional views illustrating fabrication steps of a semiconductor device according to a first preferred embodiment of the present invention. A SiO₂ layer 32 is formed on a silicon substrate 31. A SOI layer 30 is formed on the SiO₂ layer 32, as shown in FIG. 3A. Next, as shown in FIG. 3B, a nitride layer 33 is formed on the SOI layer 30. After that, as shown in FIG. 3C, the nitride layer 33 is patterned to remain regions for channel regions 34. The patterned nitride layer 33 is functioning as a mask until channel-stop ions are implanted.

According to the first preferred embodiment, STI technology is used for isolating adjacent semiconductor elements. The SOI layer 30 is etched using the nitride layer 33 as a mask to form trenches 35, as shown in FIG. 3D. Next, a field oxide layer 36 is formed in the trenches 35 by a CVD process. The field oxide layer 36 may be of SiO₂. After that, the field oxide layer 36 is polished by a CMP process, as shown in FIG. 3E. The CMP process is carried out until the nitride layer 33 is exposed so that an upper surface of the nitride layer 33 and an upper surface of the field oxide layer 36 are shaped to be the same level and flat.

Next, as shown in FIG. 3F, the field oxide layer 36 is selectively etched at an appropriate etching rate so that the SOI layer 30 and the field oxide layer 36 have substantially identical thickness. A difference in height or thickness between the SOI layer 30 and the field oxide layer 36 is removed to prevent or reduce a generation of a parasitic transistor.

Next, as shown in FIG. 3G, channel stop ions 37 are implanted into the wafer in a vertical direction. For example, BF₂⁺ ions are implanted into the field oxide layer having a thickness of 400 Å at a power of 30 keV using the nitride layer 33 as a mask. An impurity concentration of BF₂⁺ is 1.0 E 13-1.0 E 14 (ions/cm²). Such an ion implanting process is carried out according to a self-alignment of the nitride layer 33. After the ion implanting process of the impurities 37, the nitride layer 33 is removed. The above described fabrication steps are for NMOS transistor. If a PMOS transistor is fabricated, impurities of P⁺ions or arsenic ions (As⁺) would be implanted instead of BF₂⁺.

After that, well know processes, including a thermal treatment, are carried out to complete a transistor. A thermal treatment may be carried out by 800° C. to 1000° C. to diffuse the impurities 37 to ends of the channel region. An impurity concentration at the end or side portions of the channel region is increased, so that generation of a parasitic transistor at the end portions of the channel (active) region.

FIG. 4 is a graph showing an effect and advantage of the first preferred embodiment of the present invention. The graph shows variation of threshold voltage of a transistor, using STI technology, relative to a gate width. In the graph, the gate width W is indicated by LOG (logarithm) scale. In the graph, a line connecting “X” plots indicates data according to a conventional transistor, a channel stop ion is not implanted. On the other hand, a line connecting “O” plots indicates data according to the first preferred embodiment.

In general, when a width of gate of a transistor is decreased, a threshold voltage of the transistor would be decreased. As a result, a drain current would be flowing at a voltage lower than the threshold voltage, which may be called “hump” phenomenon. According to the present invention, a threshold voltage of a transistor is not lowered even if a gate width is decreased. A high impurity concentration at end portions of an active region prevents a lower of a threshold voltage of a transistor. On the other hand, according to the conventional transistor, a larger parasitic transistor is generated, so that a threshold voltage of a transistor is lowered.

FIGS. 5A-5H are cross-sectional views illustrating fabrication steps of a semiconductor device according to a second preferred embodiment of the present invention. The second preferred embodiment describes fabrication steps of a CMOS transistor. In FIGS. 5A-5H, the same or corresponding components to those shown in FIGS. 3A-3G are represented by the same reference numerals.

A SiO₂ layer 32 is formed on a silicon substrate 31. A SOI layer 30 is formed on the SiO₂ layer 32, as shown in FIG. 5A. Next, as shown in FIG. 5B, a nitride layer 33 is formed on the SOI layer 30. After that, as shown in FIG. 5C, the nitride layer 33 is patterned to remain regions for channel regions 34. The patterned nitride layer 33 is functioning as a mask until a channel-stop ion is implanted.

According to the second preferred embodiment, STI technology is used for isolating adjacent semiconductor elements. The SOI layer 30 is etched using the nitride layer 33 as a mask to form trenches 35, as shown in FIG. 5D. Next, a field oxide layer 36 is formed in the trenches 35 by a CVD process. The field oxide layer 36 may be of SiO₂. After that, the field oxide layer 36 is polished by a CMP process, as shown in FIG. 5E. The CMP process is carried out until the nitride layer 33 is exposed so that an upper surface of the nitride layer 33 and an upper surface of the field oxide layer 36 are shaped to be the same level and flat.

Next, as shown in FIG. 5F, the field oxide layer 36 is selectively etched at an appropriate etching rate so that the SOI layer 30 and the field oxide layer 36 have substantially identical thickness. A difference in height or thickness between the SOI layer 30 and the field oxide layer 36 is removed to prevent or reduce a generation of a parasitic transistor.

Next, as shown in FIG. 5G, a mask layer 38 is formed over a region for PMOS transistor, and then, channel stop ions 37 are implanted into the wafer in a vertical direction. For example, BF₂⁺ ions are implanted into the field oxide layer 36 having a thickness of 400 Å at a power of 30 keV using the mask layer 38 and the nitride layer 33 as a mask. An impurity concentration of BF₂⁺ is 1.0 E 14 (ions/cm²). Such an ion implanting process is carried out according to a self-alignment of the nitride layer 33.

Next, as shown in FIG. 5H, a mask layer 38 is formed over a region for NMOS transistor, and then, channel stop ions 137 are implanted into the wafer in a vertical direction. For example, P⁺ions or As⁺ions are implanted into the field oxide layer having a thickness of 400 Å at a power of 30 keV using the mask layer 38 and the nitride layer 33 as a mask. An impurity concentration of P⁺ is 1.0 E 14 (ions/cm²). Such an ion implanting process is carried out according to a self-alignment of the nitride layer 33. After the ion implanting process of the impurities 37, the nitride layer 33 is removed.

After that, well know processes, including a thermal treatment, are carried out to complete a transistor. A thermal treatment may be carried out by 800° C. to 1000° C. to diffuse the impurities 37 to ends of the channel regions. An impurity concentration at the end or side portions of the channel regions is increased, so that generation of a parasitic transistor at the end portions of the channel (active) regions.

According to the second preferred embodiment, threshold voltages of PMOS and NMOS transistors are not lowered even if gate widths are decreased. A high impurity concentration at end portions of active regions prevents a lower of threshold voltages of the transistors.

Claims

1. A method for fabricating a semiconductor device, comprising: providing a semiconductor substrate;forming a STI region on the semiconductor substrate;forming a channel region on the semiconductor substrate;implanting impurities into the STI region; andperforming a thermal treatment to diffuse impurities to a side of the channel region.

2. A method for fabricating a semiconductor device according to claim 1, wherein the semiconductor device is a NMOS transistor, andthe impurities is boron fluoride (BF2).

3. A method for fabricating a semiconductor device according to claim 1, wherein the semiconductor device is a PMOS transistor, andthe impurities is phosphorus ions (P+)or arsenic ions (As+).

4. A method for fabricating a semiconductor device according to claim 1, further comprising: forming an insulating layer on the semiconductor substrate; andforming a SOI layer on the insulating layer, whereinthe STI region is formed on the insulating layer.

5. A method for fabricating a semiconductor device according to claim 1, wherein the STI region is made of SiO2.

6. A method for fabricating a semiconductor device according to claim 1, wherein the impurities are implanted in a vertical direction to the STI region.

7. A method for fabricating a semiconductor device, comprising: providing a semiconductor substrate;forming an insulating layer on the semiconductor substrate;forming a SOI layer on the insulating layer;patterning a nitride layer on the SOI layer;forming a trench region and a channel region on the insulating layer using the nitride layer as a mask;forming a SiO2 layer over the entire structure including inside the trench region;removing the SiO2 layer so that the SiO2 layer, filled in the trench region, remains to form a STI region;implanting impurities into the STI region using the nitride layer as a mask;removing the nitride layer from the channel region; andperforming a thermal treatment to diffuse impurities, implanted in the STI region, to a side of the channel region.

8. A method for fabricating a semiconductor device according to claim 7, wherein the semiconductor device is a NMOS transistor, andthe impurities is boron fluoride (BF2).

9. A method for fabricating a semiconductor device according to claim 7, wherein the semiconductor device is a PMOS transistor, andthe impurities is phosphorus ions (P+)or arsenic ions (As+).

10. A method for fabricating a semiconductor device, comprising providing a semiconductor substrate;forming a STI region on the semiconductor substrate;forming a first channel region for a PMOS transistor and a second channel region for a NMOS transistor on the semiconductor substrate;masking a region for one of the PMOS and NMOS transistors;implanting first impurities into the STI region;masking a region for the other of the PMOS and NMOS transistors;implanting second impurities into the STI region; andperforming a thermal treatment to diffuse impurities to sides of the channel regions of the PMOS and NMOS transistors.

11. A method for fabricating a semiconductor device according to claim 10, wherein the first and second impurities are boron fluoride (BF2) and phosphorus (P+) or arsenic (As+), the boron fluoride (BF2) ions being implanted in the NMOS region and phosphorus or arsenic (As+) ions being implanted in the PMOS region.

12. A method for fabricating a semiconductor device according to claim 10, further comprising: forming an insulating layer on the semiconductor substrate; andforming a SOI layer on the insulating layer, whereinthe STI region is formed on the insulating layer.

13. A method for fabricating a semiconductor device according to claim 10, wherein the STI region is made of SiO2.

14. A method for fabricating a semiconductor device according to claim 10, wherein the first and second impurities are implanted in a vertical direction to the STI region.