The present application claims priority to Korean Patent Application No. 10-2021-0029459, filed on Mar. 5, 2021, which is herein incorporated by reference in its entirety.
The present invention relates to a semiconductor device, and, more particularly, to a method for fabricating the semiconductor device including a silicide.
A metal silicide is formed to suppress the leakage current and an increase of the contact resistance during a semiconductor device fabrication. A contact structure has become finer, as semiconductor devices become smaller. That is, an open area of a contact hole has decreased, and a height of a contact hole has gradually increased.
Accordingly, there is a need for an improved method for further lowering the contact resistance as the semiconductor device becomes smaller.
Various embodiments of the present invention provide a method of fabricating a semiconductor device capable of improving the contact resistance.
According to an embodiment of the present invention, a method for fabricating a semiconductor device comprises: forming a doped region by doping and activation annealing a first dopant on a substrate; forming an interlayer insulating layer on the substrate; forming a contact hole exposing the doped region by etching the interlayer insulating layer; exposing the doped region to a pre-annealing; forming an additional doped region by doping a second dopant on a pre-annealed doped region; exposing the additional doped region to a post-annealing; and forming metal silicide on the additional doped region.
According to an embodiment of the present invention, a method for fabricating a semiconductor device comprises: forming an N-type source/drain region and a P-type source/drain region in a substrate; forming an interlayer insulating layer on the substrate; forming a contact hole respectively exposing the N-type source/drain region and the P-type source/drain region by etching the interlayer insulating layer; exposing the N-type and P-type source/drain regions to a pre-annealing; forming an N-type additional doped region by doping an N-type additional dopant in an annealed N-type source/drain region; forming a P-type additional doped region by doping a P-type additional dopant in an annealed P-type source/drain region; exposing the N-type and P-type additional doped regions to a post-annealing; and forming a metal silicide on each of he annealed N-type and P-type additional doped regions.
According to an embodiment of the present invention, a method for fabricating a semiconductor device comprises: forming an N-type source/drain region and a P-type source/drain region in a substrate; forming an interlayer insulating layer on the substrate; forming a contact hole respectively exposing the N-type source/drain region and the P-type source/drain region by etching the interlayer insulating layer; forming an N-type additional doped region by doping an N-type additional dopant in the N-type source/drain region; exposing the N-type additional doped region, the N-type source/drain region, and the P-type source/drain region to a pre-annealing; forming a P-type additional doped region by doping a P-type additional dopant in an annealed P-type source/drain region; exposing the N-type and P-type additional doped regions to the post-annealing; and forming a metal silicide on each of annealed N-type and P-type additional doped regions.
The present disclosure can improve the contact resistance of a source/drain region and a metal silicide by performing a pre-annealing process before an additional doping process and performing a post-annealing process after the additional doping process.
The present disclosure can improve the P-type contact resistance without deteriorating the N-type contact resistance by performing a high-temperature pre-annealing process before or after the additional doping process of the N-type dopant and by performing a low-temperature post-annealing process after an additional doping process of the P-type dopant.
The present disclosure can improve an operation speed of a semiconductor device and suppress leakage.
Various embodiments described herein will be described with reference to cross-sectional views, plane views and block diagrams, which are ideal schematic views of the present invention. Therefore, the structures of the drawings may be modified by fabricating technology and/or tolerances. The embodiments of the present invention are not limited to the specific structures shown in the drawings, but include any changes in the structures that may be produced according to the fabricating process. Also, any regions and shapes of regions Illustrated in the drawings have schematic views, are intended to illustrate specific examples of structures of regions of the various elements, and are not intended to limit the scope of the invention.
Referring to
Referring to
The source/drain regions 108 may be formed on both sides of the gate stack Gin the active region 103. The source/drain regions 108 may be doped with a first dopant. The first dopant may include an N-type dopant. The first dopant may include a P-type dopant. An insulating layer 109 may be formed over the substrate 101. The insulating layer 109 may include contact holes 110 each passing through the insulating layer 109 to expose a corresponding one of the source/drain regions 108. An additional doped region 111 may be formed over a surface of the source/drain region 108. The additional doped region 111 may be doped with a second dopant. The second dopant may include an N-type dopant or a P-type dopant. The first dopant and the second dopant may be the same or different from each other. The contact hole 110 may expose a surface of the additional doped region 111. A metal silicide 112 may be formed on the surface of the additional doped region 111. A contact plug 113 may be formed on the metal silicide 112. The contact plug 113 may fill the contact hole 110.
As the additional doped region 111 is formed between the metal silicide 112 and the source/drain region 108, contact resistance may be improved.
As will be described later, the additional doped region 111 is carbon-free and fluorine-free, i.e., it may contain neither carbon nor fluorine. The additional doping process S104 may be performed to form the additional doped region 111 following the pre-annealing process S103. Post-annealing process S105 may also be performed after the additional doping process S104. Damages generated on the surface of the source/drain regions 108 during the forming of the contact hole S102 may be removed by the pre-annealing process S103.
The pre-annealing and the post-annealing process S103 and S105 may be performed at different temperatures. The method of heat treatment during the pre-annealing and the post-annealing process S103 and S105 may be of the same type but at different temperatures for each process. For example, the pre-annealing process S103 and the post-annealing process S105 may both include a rapid thermal process (RTP), however, the pre-annealing process S103 may be performed at a temperature higher than 950° C., while the post-annealing process S105 may be performed at a temperature of 950° C. or less. Performing the post-annealing process 25 at a temperature of 950° C. or less may be advantageous because it may suppress diffusion of impurities which are doped in the additional doped region 111.
In another embodiment, the pre-annealing process S103 and the post-annealing process S105 may be performed using different type thermal processes. For example, the pre-annealing process S103 may be performed by employing a rapid thermal process (RTP) such as a spike-rapid thermal annealing (spike-RTA), while the post-annealing process S105 may be performed by laser annealing or milli-second annealing. The post-annealing process S105 may be performed for a shorter time than the pre-annealing process S103. The pre-annealing process S103 and the post-annealing process S105 may each be performed at a temperature higher than 950° C., but the post-annealing process S105 may be performed at a temperature higher than the pre-annealing process S103 for less than about 1 second. Performing the post-annealing process S105 only for a short time of less than 1 second (for example for a few milliseconds) may suppress diffusion of dopants which are doped in the additional doped region 111. Short time annealing may be also referred to as milli-second annealing and may be advantageous over the rapid thermal process annealing. This is because, milli-second annealing is performed at a higher temperature than the rapid thermal process and for a very short time and, thus, diffusion of dopants may be further suppressed or minimized.
As shown in
A gate stack G may be formed over the substrate 11. The gate stack G may include a gate insulating layer 14, a gate electrode 15, and a gate capping layer 16. A spacer 17 may be formed on both sidewalls of the gate stack G.
The gate insulating layer 14 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. The high-k material may include a material having a dielectric constant greater than a dielectric constant of silicon oxide. For example, the high-k material may include a material having a dielectric constant greater than 3.9. In another example, the high-k material may include a material having a dielectric constant greater than 10. In another example, the high-k material may include a material having a dielectric constant of 10 to 30. The high-k material may include at least one metallic element. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In another embodiment, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, and a combination thereof. Other known high-k materials may be selectively used as a high-k material. The gate insulating layer 14 may be formed by stacking an interface layer and a high-k material. The interface layer may include silicon oxide, and the high-k material may include a hafnium-based material.
The gate electrode 15 may include one or more conductive materials, such as doped polysilicon, metal, metal alloy, silicide, or other suitable conductive materials. The gate electrode 15 may include a multi-layer structure having a multi-metal material. In another embodiment, the gate electrode 15 may include a material whose work function is tuned to obtain an improved threshold voltage. In some embodiments, the gate electrode 15 may be a material having a work function (4.5 eV or less) for an N-channel transistor. In another embodiment, the gate electrode 15 may be a material having a work function (4.5 eV or more) for a P-channel transistor. The gate capping layer 16 may include silicon oxide, silicon nitride, or a combination thereof. The spacer 17 may include silicon oxide, silicon nitride, or a combination thereof.
Doped regions may be formed in the active region 13 of the substrate 11. The doped regions may include a first source/drain region 18A and a second source/drain region 19A spaced apart from each other.
The first source/drain region 18A and the second source/drain region 19A may be formed by a doping process such as an implantation process. The first source/drain region 18A and the second source/drain region 19A may be doped with a first dopant such as an N-type dopant or a P-type dopant. For example, the first dopant may include phosphorus (P), arsenic (As), antimony (Sb), or boron (B). The first source/drain region 18A and the second source/drain region 19A may be doped with the first dopant of the same conductivity type. The first source/drain region 18A and the second source/drain region 19A may be an N-type source/drain region or a P-type source/drain region. The first source/drain region 18A and the second source/drain region 19A may include deep regions 18D and 19D, respectively, and shallow regions 18S and 19S, respectively. The shallow regions 18S and 19S may be referred to as a lightly doped drain (LDD) or a source drain extension (SDE). The shallow regions 18S and 19S may have a lower dopant concentration than the deep regions 18D and 19D. The shallow regions 18S and 19S may partially overlap with the gate stack G and the spacer 17. The shadow regions 18S and 19S may be spaced apart from each other leaving a region of the active region 13 between them positioned below the gate insulating layer 14 that is not doped. The shallow regions 18S and 19S may extend at a lower depth inside the substrate 11 than the deep regions 18D and 19D.
To form the first and second source/drain regions 18A and 19A, a doping process using the first dopant followed by activation annealing of the first dopant may be sequentially performed. Activation annealing may include rapid thermal annealing (RTA) at a temperature of 1000° C. or higher for a few seconds or less. The first and second source/drain regions 18A and 19A may include activated first dopants by activation annealing.
As shown in
As shown in
The contact etching process for forming the contact hole 21 may be performed using an etching gas including carbon (C), fluorine (F), or a combination thereof. For example, during the contact etching process, the etching gas may include a mixed gas of C4F8/Ar/O2.
As described above, the contact etching process uses an etching gas containing carbon and fluorine, and a damaged portion 21D may be formed on the top surfaces of the first and second source/drain regions 18A and 19A, the damaged portion 21D being damaged by and containing carbon and fluorine. The damaged portion 21D may include substrate loss or a lattice defect. When the damaged portion 21D contains a large amount of carbon and fluorine, contact resistance may be deteriorated.
As shown in
As the pre-annealing process 22 is performed, the pre-annealed first and second source/drain regions 18B and 19B may become carbon-free and fluorine-free surfaces.
As shown in
The additional doping process 23 may include implanting a second dopant on the substrate 11. The additional doping process 23 may be performed on surfaces of the pre-annealed first and second source/drain regions 18B and 19B. After the additional doping process 23 is performed, the pre-annealed first and second source/drain 18B and 19B may be referred to as an additional-doped first and second source/drain 18C and 19C. An additional doped region 24′ may be formed in the surfaces of the additional-doped first and second source/drain regions 18C and 19C by the additional doping process 23. When the additional-doped first and second source/drain regions 18C and 19C are doped with an N-type dopant, the additional doping process 23 may employ dopants such as P, As, or Sb. The additional doped region 24′ may include N-type dopants having a higher concentration than the additional-doped first and second source/drain regions 18C and 19C.
In another embodiment, when the additional-doped first and second source/drain regions 18C and 19C are doped with a P-type dopant, the additional doping process 23 may include two doping processes. For example, a first additional doping process and a second additional doping process may be sequentially performed. The first and second additional doping processes may employ different second dopants. For example, the first additional doping process may use germanium, and the second additional doping process may use a P-type dopant such as boron. The first additional doping process may be performed with a germanium implantation, which may be referred to as a germanium pre-amorphous implantation (Ge PAI). In the case of the germanium implant, the degree of activation of the dopant in the additional-doped first and second source/drain regions 18C and 19C may be improved, and diffusion of the dopant may be controlled. In the second additional doping process, the boron-based material may be doped. The boron-based material may include B, BF2, BF3 or B2H6. The second additional doping process may be performed by an implantation process or plasma doping (PLAD). For example, in the case of B2H6, a large amount of boron may be doped in a short time through plasma doping (PLAD), and contact resistance characteristics are also very excellent. In another embodiment, an additional doping of germanium may be performed after the additional doping process of boron. In another embodiment, after omitting the first additional doping process, only the second additional doping process may be performed. When the additional-doped first and second source/drain regions 18C and 19C and the additional doped regions 24′ are doped with a P-type dopant, the additional doped regions 24′ may have a higher concentration of P-type dopants than the additional-doped first and second source/drain regions 18C and 19C.
As shown in
As a comparative example, when the pre-annealing process 22 is omitted and the post-annealing process 25 is performed by a rapid thermal process at a temperature above 950° C., the dopants may be out-diffused from the surfaces of the post-annealed first and second source/drain regions 18 and 19, thereby deteriorating the contact resistance.
As another comparative example, when both the pre-annealing process 22 and the post-annealing process 25 are performed by a rapid thermal process at a temperature above 950° C., the dopants may be out-diffused from the surfaces of the post-annealed first and second source/drain regions 18 and 19.
The post-annealing process 25 may be performed at a temperature in the range of 850° C. to 950° C.
Both the pre-annealing process 22 and the post-annealing process 25 may be performed by a rapid thermal process.
In another embodiment, the pre-annealing process 22 and the post-annealing process 25 may be performed with different types of thermal processes. For example, the pre-annealing process 22 may be performed by a spike-rapid thermal process, and the post-anneal 25 may be performed by laser annealing or milli-second annealing. The post-annealing process 25 may be performed in a shorter time than the pre-annealing process 22. The pre-annealing process 22 and the post-annealing process 25 each may be performed at a temperature above 950° C., but the post-annealing process 25 may be performed at a temperature higher than the pre-annealing process 22 for a time of less than about 1 second. Since the post-annealing process 25 is performed for a short time of less than 1 second, diffusion of the dopants doped to the post-annealed additional doped region 24 may be suppressed. Because the milli-second annealing anneals for a short time and uses a higher temperature than the spike-rapid thermal process, diffusion of the dopants may be minimized.
As shown in
As shown in
According to the above-described embodiment, a large amount of attack caused during a contact etching process for forming the contact hole 21 may be cured. For example, the contact etching process uses an etching gas containing carbon, fluorine, and so on. The damaged portion 21D caused by and containing the carbon and the fluorine may be formed on the surfaces of the first and second source/drain regions 18A and 19A. By performing the pre-annealing process 22, the damaged portion 21D may be cured, and deactivation of the pre-annealed first and second source/drain regions 18B and 19B may be compensated. Consequently, it is possible to increase the speed by improving the drive current and the contact resistance through the pre-annealing process 22. In addition, it is possible to improve leakage by reducing band-to-band tunneling or trap assisted tunneling through the pre-annealing process 22.
The dopant concentration of the surfaces of the post-annealed first and second source/drain regions 18 and 19 may be secured by the post-annealing process 25. Accordingly, contact resistance may be improved by increasing the dopant concentration at interfaces between the post-annealed first source/drain region 18 and the metal silicide 26 and between the post-annealed second source/drain region 19 and the metal silicide 26. In addition, the change in the threshold voltage may be reduced by reducing diffusion of dopants from the post-annealed first and second source/drain regions 18 and 19 to an edge of the gate electrode 15 through the post-annealing process 25.
In this embodiment, the contact resistances of the post-annealed first and second source/drain regions 18 and 19 and the contact resistance of the metal silicide 26 may be improved by performing the pre-annealing process 22 before the additional doping process 23 and by performing the post-annealing process 25 after the additional doping process 23. In addition, in this embodiment, the contact resistance may be improved even if the contact areas between the post-annealed first source/drain region 18 and the metal silicide 26 and between the post-annealed second source/drain region 19 and the metal silicide 26 decrease, and the gap between the contact plug 26 and the gate stack G decreases.
As shown in
A plurality of gate stacks NG and PG may be formed over the substrate 11. The gate stacks NG and PG may include an N-type gate stack NG and a P-type gate stack PG. The N-type gate stack NG may be formed on the NMOS region NMOS of the substrate 11. The P-type gate stack PG may be formed on the PMOS region PMOS of the substrate 11. The N-type gate stack NG may include a gate insulating layer 14, an N-type gate electrode 15N, and a gate capping layer 16. A spacer 17 may be formed on both sidewalls of the N-type gate stack NG. The P-type gate stack PG may include the gate insulating layer 14, a P-type gate electrode 15P, and the gate capping layer 16. A spacer 17 may be formed on both sidewalls of the P-type gate stack PG.
The gate insulating layer 14 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. The gate insulating layer 14 may be formed by stacking an interface layer and a high-k material. The gate capping layer 16 may include silicon oxide, silicon nitride, or a combination thereof. The spacer 17 may include silicon oxide, silicon nitride, or a combination thereof.
The N-type gate electrode 15N and the P-type gate electrode 15P may include one or more conductive materials, such as doped polysilicon, metal, metal alloy, silicide, or other suitable conductive materials. The N-type gate electrode 15N may be a material having a work function of 4.5 eV or less for an N-channel transistor, and the P-type gate electrode 15P may be a material having a work function of 4.5 eV or more for a P-channel transistor.
N-type and P-type source/drain regions 18N and 18P may be formed in the active region 13 of the substrate 11. The N-type source/drain region 18N may be formed in the active region 13 of the NMOS region NMOS, and the P-type source/drain region 18P may be formed in the active region 13 of the PMOS region PMOS.
The N-type source/drain region 18N may be doped with an N-type dopant, and the P-type source/drain region 18P may be doped with a P-type dopant. The N-type source/drain regions 18N may include deep regions 18ND and 19ND and shallow regions 18NS and 19NS. The P-type source/drain regions 18P may include deep regions 18PD and 19PD and shallow regions 18PS and 19PS. The shadow regions 18NS, 19NS, 18PS, and 19PS may be referred to as a lightly doped drain (LDD) or a source drain extension (SDE). The shallow regions 18NS, 19NS, 18PS, and 19PS may have a lower dopant concentration than the deep regions 18ND, 19ND, 18PD, and 19PD. The shallow regions 18NS, 19NS, 18PS, and 19PS may extend to a lower depth inside the substrate 11 than the deep regions 18ND, 19ND, 18PD, and 19PD. The shallow regions 18NS, 19NS, 18PS, and 19PS may partially overlap with respective gate stacks and spacers 17.
In order to form the N-type source/drain regions 18N and the P-type source/drain regions 18P, a dopant doping process and activation annealing may be sequentially performed. The activation annealing may include rapid thermal annealing (RTA) at a temperature of 1000° C. or higher.
As shown in
Next, a contact etching process may be performed to form a contact hole 21 in the interlayer insulating layer 20. The contact hole 21 may expose portions of the N-type and P-type source/drain regions 18N and 18P. The contact hole 21 may be formed by photolithography and etching processes. In an embodiment, a patterned photoresist (not shown) may be formed, and the interlayer insulating layer 20 may be etched by a contact etching process using the patterned photoresist as an etching mask.
The contact etching process for forming the contact hole 21 may be performed using an etching gas including carbon (C), fluorine (F), or a combination thereof. For example, during the contact etching process, the etching gas may include a mixed gas of C4F8/Ar/O2.
As described above, the contact etching process uses an etching gas containing carbon, fluorine, etc., and a damaged portion 21D caused by and containing the carbon and the fluorine may be formed on surfaces of the N-type and P-type source/drain regions 18N and 18P. The damaged portion 21D may include substrate loss or lattice defect. When the damaged portion 21D contains a large amount of carbon and fluorine, contact resistance may be deteriorated.
As shown in
As shown in
The first additional doping process 23N may be performed to implant an additional dopant on the substrate 11. The first additional doping process 23N may be performed on the surface of the N-type source/drain region 18N. An N-type additional doped region 24N may be formed in the surface of the N-type source/drain region 18N through the first additional doping process 23N. In order to form the N-type additional doped region 24N, the doping process may be performed with an N-type dopant such as P, As, or Sb.
As shown in
The second additional doping process 23P may include two doping processes. For example, a germanium doping process and a boron doping process may be sequentially performed. The germanium doping process may be performed with a germanium implantation, and the boron doping process may be doped with a boron-based material such as B, BF2, BF3 or B2H6. The boron doping process may be performed by an implantation process or plasma doping (PLAD). For example, the boron doping process may be performed by B2H6 plasma doping (PLAD). In another embodiment, the germanium doping process may be performed after the boron doping process.
A P-type additional doped region 24P may be formed in the surface of the P-type source/drain region 18P by the second additional doping process 23P. The P-type additional doped region 24P may be doped with germanium and boron.
As shown in
In another embodiment, the pre-annealing process 22 and the post-annealing process 25 may be performed with different types of thermal process. For example, the pre-annealing process 22 may be performed by a spike rapid thermal process, and the post-annealing process 25 may be performed by laser annealing or milli-second annealing. The post-annealing process 25 may be performed for a shorter time than the pre-annealing process 22. The pre-annealing process 22 and the post-annealing process 25 each may be performed at a temperature higher than 950° C., but the post-annealing process 25 may be performed at a temperature higher than the pre-annealing process 22 for a time of less than about 1 second. Since the post-annealing process 25 is performed for a short time of less than 1 second, diffusion of dopants doped in the N-type and P-type source/drain regions 18N and 18P may be suppressed. The milli-second annealing has a higher temperature than the spike-rapid thermal process and is annealing for a short time, so diffusion of dopants may be minimized.
As shown in
Next, the contact plug 27 may be formed. The contact plug 27 may include at least one of tungsten, titanium, and titanium nitride. The metal silicide 26 may contact the contact plug 27.
Referring to
The contact etching process for forming the contact hole 21 may be performed using an etching gas including carbon (C), fluorine (F), or a combination thereof. For example, during the contact etching process, the etching gas may include a mixed gas of C4F8/Ar/O2.
As above, the contact etching process uses an etching gas containing carbon, fluorine, and so on. A damaged portion 21D caused by and containing the carbon and the fluorine may be formed on surfaces of the N-type and P-type source/drain regions 18N and 18P. The damaged portion 21D may include a substrate loss or a lattice defect. When the damaged portion 21D contains a large amount of carbon and fluorine, contact resistance may be deteriorated.
As shown in
The first additional doping process 23N may be performed to implant an additional dopant on the substrate 11. The first additional doping process 23N may be performed on a surface and the damaged portion 21D of the N-type source/drain region 18N. An N-type additional doped region 24N may be formed in the surface of the N-type source/drain region 18N by the first additional doping process 23N. The N-type additional doped region 24N may be doped with an N-type dopant such as P, As, or Sb.
As shown in
As shown in
The second additional doping process 23P may include two doping processes. For example, a germanium doping process and a boron doping process may be sequentially performed. The germanium doping process may be performed with a germanium implantation, and the boron doping process may be doped with a boron-based material such as B, BF2, BF3 or B2H6. The boron doping process may be performed by an implantation process or plasma doping (PLAD). For example, the boron doping process may be performed by B2H6 plasma doping (PLAD). In another embodiment, the germanium doping process may be performed after the boron doping process.
A P-type additional doped region 24P may be formed in the surface of the P-type source/drain region 18P by the second additional doping process 23P. The P-type additional doped region 24P may be doped with germanium and boron.
As shown in
In another embodiment, the pre-annealing process 22 and the post-annealing process 25 may be performed with different types of thermal processes. For example, the pre-annealing process 22 may be performed by spike-rapid thermal annealing. The post-annealing process 25 may be performed by laser annealing or milli-second annealing. The post-annealing process 25 may be performed for a shorter time than the pre-annealing process 22. The pre-annealing process 22 and the post-annealing process 25 may be performed at a temperature higher than 950° C., but the post-annealing process 25 may be performed at a temperature higher than the pre-annealing process 22 for a time of less than about 1 second. Since the post-annealing process 25 is performed for a short time of less than 1 second, diffusion of dopants doped in the N-type and P-type source/drain regions 18N and 18P may be suppressed. The milli-second annealing is performed at a higher temperature than the spike-rapid heat treatment and for a short time, so diffusion of dopants may be minimized.
Subsequently, as shown in
In the embodiments according to
In the present embodiments, as the pre-annealing process 22 is performed before or after the first additional doping process 23N and the post-annealing process 25 is performed after the second additional doping process 23P, the P-type contact resistance may be improved without deterioration of the N-type contact resistance.
The CMOSFET of the above-described embodiments may be applied as a part of a memory device, a logic device, or the like. For example, it may be applied as a peripheral circuit transistor of a memory device such as a dynamic random-access memory (DRAM), NAND, and a phase-change random-access memory (PCRAM). The memory cell array of the DRAM or the memory cell string of the NAND may be controlled by a peripheral circuit transistor.
Referring to
The cell region CELL may include a bit line structure BLS and a storage node contact plug SNC formed on the substrate 11, a buried word line BWL buried in the substrate 11, and a capacitor CAP formed on the storage node contact plug SNC. The bit line structure BLS may have a stack structure of a bit line contact plug BLC, a bit line BL, and a bit line hard mask BLH. The storage node contact plug SNC may include a lower plug PP, an upper plug 27C on the lower plug PP, a landing pad LP on the upper plug 27C, and an ohmic contact layer 26C between the upper plug 27C and the lower plug PP. The lower plug PP may include doped polysilicon. The upper plug 27C and the landing pad LP may include a metal-based material. The ohmic contact layer 26C may include metal silicide such as cobalt silicide.
A detailed description of the transistors formed in the peripheral circuit area PERI will be described with reference to
In another embodiment, the N-type metal layer 15N and the P-type metal layer 15P may be the same metal material. In this case, the N-type gate stack NG and the P-type gate stack PG may be engineered to have an N-type effective work function and a P-type effective work function, respectively. For example, in the N-type gate stack NG, an N-type capping layer may be formed between the gate insulating layer 14 and the polysilicon 15S. In the P-type gate stack PG, the P-type gate capping layer may be formed between the gate insulating layer 14 and the polysilicon 15S. The N-type capping layer may include lanthanum or lanthanum oxide, and the P-type capping layer may include aluminum or aluminum oxide.
An N-type additional doped region 24N may be formed on the surface of the N-type source/drain region 18N, and a P-type additional doped region 24P may be formed on the surface of the P-type source/drain region 18P. Metal silicide 26 may be formed on both the N-type additional doped region 24N and the P-type additional doped region 24P. A contact plug 27 may be formed on the metal silicide 26, and a metal interconnection 28 may be formed on the contact plug 27. The contact plug 27 and the metal interconnection 28 may be, for example, a stack structure of titanium nitride and tungsten (TiN/W).
The polysilicon 15S of the N-type gate stack NG and the P-type gate stack PG may be made of the same material also used for the bit line contact plug BLC. The N-type metal layer 15N of the N-type gate stack NG and the P-type metal layer 15P of the P-type gate stack PG may be made of the same material also used for the bit line BL.
The ohmic contact layer 26C of the storage node contact plug SNC and the metal silicide 26 of the peripheral circuit region PERI may be formed at the same time. The upper plug 27C of the storage node contact plug SNC and the contact plugs 27 of the peripheral circuit region PERI may be formed at the same time. The landing pad LP of the storage node contact plug SNC and the metal interconnection 28 of the peripheral circuit region PERI may be formed at the same time.
While forming the N-type and P-type additional doped regions 24N and 24P, additional dopants may be doped on the surface of the lower plug PP of the cell region CELL. For example, while forming the N-type additional doped region 24N, a cell additional doped region 24C may be formed by doping N-type additional dopants on the surface of the lower plug PP.
The above-described invention is not limited by the above-described embodiments and the accompanying drawings. It will readily be appreciated by one of ordinary skill in the art that various substitutions, changes, or modifications may be made thereto without departing from the scope of the disclosure.
Number | Date | Country | Kind |
---|---|---|---|
10-2021-0029459 | Mar 2021 | KR | national |