The present invention broadly relates to lithographic printing of features for forming integrated circuit (IC) patterns on a semiconductor chip, and particularly to improvements in selecting and using combinations of illumination source characteristics and diffracting shapes on a reticle mask, and more particularly to improvements in identifying and prioritizing portions of an IC design on which to perform optimization of the lithographic process more cost effectively.
In the manufacture of integrated circuits, photolithographic processes are commonly used, in which a wafer is patterned by projecting radiation through a patterned mask to form an image pattern on a photo sensitive material, referred to as a photoresist, or simply resist. The exposed resist material is developed to form openings corresponding to the image pattern, and then the pattern is transferred to the wafer substrate by methods such as etching, as known in the art.
Many methods have been developed to compensate for the image degradation that occurs when the resolution of optical lithography systems approaches the critical dimensions (CD's) of desired lithographic patterns that are used to form devices and integrated circuits (IC's) on a semiconductor chip. Critical dimension (CD) refers to the feature size and spacing between features and feature repeats (pitch) that are required by the design specifications and are critical for the proper functioning of the devices on a chip. When the CD's of a desired IC pattern approach the resolution of a lithographic system (defined as the smallest dimensions that can be reliably printed by the system), image distortions becomes a significant problem. Today the limited resolution of lithography tools poses a key technical challenge in IC manufacture, and this difficulty will increase in the future as critical dimensions become increasingly smaller. In order to make the manufacture of future IC products feasible, lithography tools will be required to achieve adequate image fidelity when the ratio of minimum CD to resolution of the lithographic system is very low.
The basic lithography system consists of a light source, a photomask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the mask. The mask design process as described herein covers the steps from chip design, model-based optical proximity correction (MBOPC), OPC Verification and mask fabrication.
The resolution ρ of a lithographic system can be described by the equation:
where ρ is the minimum feature size that can be lithographically printed, λ is the wavelength of the light source used in the projection system and NA (numerical aperture) is a measure of the amount of light that can be collected by the projection optics. k1 is a factor that represents aspects of the lithographic process other than wavelength or numerical aperture, such as resist properties or the use of enhanced masks. When the illumination source is partially coherent, k1 may expressed as 1/[2(σ+1)], where σ is a measure of the partial coherence of the source, where σ has a value between 0 and 1. Typical values for k1 range from about 0.7 to 0.3.
Low k1 patterning is typically extremely sensitive to fluctuations in lithographic parameters such as dose, mask CD, focus, etc., which leads to small process windows. Methods have been proposed for optimizing combinations of source illumination and mask patterns (referred to hereinafter as source-mask optimization or “SMO”) together can result in improved process windows (see, for example, U.S. Pat. No. 6,563,566). However, SMO methods are very computationally expensive and it is impractical to perform SMO on a full chip layout. Thus, only selected “hard-to-print” patterns from the full chip layout should be considered for full optimization by computationally intensive methods such as SMO.
Currently, so-called “hard-to-print” patterns are identified using a set of predetermined rules that are determined experimentally for a specific chip design. However, such rules are not applicable in general cases. Other methods rely on an approximate imaging methods that are too slow for many applications.
In view of the above, there is a need for a fast method to identify “hard-to-print” patterns that can be prioritized for processing with full optimization methods.
The present invention provides a method and computer program product for designing an integrated circuit layout, comprising the steps of providing a plurality of layouts of features to be printed, determining the diffraction orders in spatial frequency space for each of the plurality of layouts, providing a lithographic difficulty metric, computing, for each of the plurality of layouts, values of the lithographic difficulty metric, and evaluating each of the plurality of layouts based on the values of the lithographic difficulty metric.
The inventive lithographic difficulty metric is a function of an energy ratio factor comprising a ratio of hard-to-print energy to easy-to-print energy of said diffraction orders along an angular coordinate θi of spatial frequency space, wherein the hard-to-print energy comprises energy of the diffraction orders at values of the normalized radial coordinates r of spatial frequency space in a neighborhood of r=0 and in a neighborhood of r=1, and the easy-to-print energy comprises energy of the diffraction orders located at intermediate values of the normalized radial coordinates r between the neighborhood of r=0 and the neighborhood of r=1, an energy entropy factor comprising energy entropy of the diffraction orders along the angular coordinate θi, a phase entropy factor comprising phase entropy of the diffraction orders along the angular coordinate and θi; and a total energy entropy factor comprising total energy entropy of the diffraction orders.
According to one aspect of the invention, the method further comprises performing full optimization processing on each of the plurality of layouts having a value of the lithographic difficulty metric that is greater than a predetermined lithographic difficulty threshold.
According to another aspect of the invention, the plurality of layouts comprises a set of unique tiles of patterns of features such that a full chip layout consists of an arrangement of a plurality of tiles selected from the set of unique tiles.
The predetermined lithographic difficulty threshold may be typically set to identify which of the unique tiles in said set of unique tiles are binding patterns of the full chip layout.
According to yet another aspect of the invention, the computed values of the lithographic difficulty metric are computed at selected values of the angular coordinate θi, and the method further comprises determining a global lithographic difficulty metric for each of the plurality of layouts, the global lithographic difficulty metric comprising a maximum value of the lithographic difficulty metrics from among the selected values of the angular coordinate θi.
In another aspect, a method of designing an integrated circuit layout is provided, comprising the steps of: providing a set of design tiles, wherein each of the design tiles in the set comprises a unique layout of patterns of features to be printed; providing a plurality of chip layouts, wherein each of the chip layouts consists of an arrangement of tiles selected from the set of design tiles; providing a lithographic difficulty metric. The method further includes, for each of the chip layouts, performing the method steps of: determining the diffraction orders in spatial frequency space for each unique tile in the arrangement of tiles; computing, for each of the unique tiles in the arrangement of tiles, values of the lithographic difficulty metric; evaluating each of the unique tiles based on the values of the lithographic difficulty metric.
The method according to the invention may be implemented in a computer program product and a computer system comprising a computer useable medium including computer readable instructions, wherein the computer readable instructions, when executed on a computer causes the computer or computer system to perform the method steps of providing a plurality of layouts of features to be printed, determining the diffraction orders in spatial frequency space for each of the plurality of layouts, providing a lithographic difficulty metric, computing, for each of the plurality of layouts, values of the lithographic difficulty metric, and evaluating each of the plurality of layouts based on the values of said lithographic difficulty metric.
The foregoing and other features and advantages of the invention will be apparent from the following detailed description of the invention.
Referring to the exemplary drawings wherein like elements are numbered alike in the several figures, not necessarily drawn to scale, in which:
This invention presents a method and apparatus for designing and optimizing layouts for use in the manufacture of integrated circuits, and more particularly, for identifying and prioritizing portions of such layouts for which a full optimization methodology is to be performed.
The basic components of a projection lithographic system are illustrated in
The pattern of features on the reticle 120 acts as a diffracting structure analogous to a diffraction grating which transmits radiation patterns that may interfere constructively or destructively. This pattern of constructive and destructive interference can be conveniently described in terms of a Fourier transform in direction space (or equivalently also referred to herein as spatial frequency space) based on spacing of the features of the diffraction grating (or reticle 120). The Fourier components of diffracted energy associated with the spatial frequencies of the diffracting structure are known in the art as diffracted orders. For example, the zeroth order is associated with the direct current (DC) component, but higher orders are related to the wavelength of the illuminating radiation and inversely related to the spacing (known as pitch) between repeating diffracting features. When the pitch of features is smaller, the angle of diffraction is larger, so that higher diffracted orders will be diffracted at angles larger than the numerical aperture of the lens.
A diagram can be constructed in direction space to indicate the diffracted orders that can be collected by a lithographic system that is based on repeating dimensions of a desired pattern. For example, consider a unit cell pattern illustrated in
The diffraction orders a(ux, uy) may also be represented in terms of radial coordinates in spatial frequency space, as in:
a(ux,uy)=a(r∠θ) Eq. 2
where r is the radial coordinate in direction space and θ is the angular coordinate in direction space.
A chip design layout typically contains millions of features, many of which are arranged in patterns that may be repeated throughout the chip layout. Although it may be desirable to perform an optimization of the entire chip as a single unit, a full optimization of the whole chip is not practical due to limitations such as computer memory, computation time and cost. For the purposes of optimization, it is useful to subdivide and classify the entire layout into a small, computationally practical number of unique patterns or “tiles” of features that, when assembled together, exhaustively represent the chip layout. Preferably, a minimum tile size contains a set of features such that a feature located at the edge of a tile is within the optical radius of influence (ROI) around a feature located at the center of the tile. The ROI is the distance at which a feature located outside the ROI would not substantially affect, within a predetermined variability tolerance, the printing of the target (e.g. center) feature. For example, the ROI may be set to be a region having a radius wherein a feature located outside the ROI would influence the printed size of a feature at the center of the tile by less than a variability tolerance of 5%. A maximum tile size is chosen according to practical limitations, such as memory, CPU or turnaround time requirements and cost. Any method now known or developed in the future may be used to identify such tiles. As discussed further below, many of the tiles may represent patterns that are repeated throughout the layout, so that an analysis, in accordance with the invention, of one such tile only needs to be performed once for the entire layout.
In accordance with the invention, a lithographic difficulty (equivalently referred to as “litho difficulty”) metric LD is defined for a given tile j that provides a measure of the relative distribution of energy in relatively “hard-to-print” patterns versus relatively “easy-to-print” patterns within the jth tile. Furthemore, the litho difficulty metric is defined along a given angular coordinate θi of the unit circle in direction space, where for convenience, hereinafter, the index i equivalently refers to a given angular coordinate θi. The litho difficulty metric LDij for the jth tile in the ith region is a function of four factors: 1) an energy ratio factor Aij (see Eq. 3) representing a ratio of “hard” to print versus “easy” to print diffracted energy along an angular coordinate θi in spatial frequency space for the jth tile; 2) an energy entropy factor Be,ij (see Eq. 4) representing a (typically normalized) measure of energy entropy along an angular coordinate θi in spatial frequency space for jth tile; 3) a phase entropy factor Bφ,ij (see Eq. 5) representing a measure of phase entropy along an angular coordinate θi in spatial frequency space for the jth tile; and 4) a total energy entropy factor ETj (see Eq. 6) representing a measure of the total energy entropy for the jth tile.
The energy ratio factor Aij is defined as
where Wij(r) is an amplitude factor proportional to the energy of the diffraction orders along a given angular coordinate θi in direction space, fIMH(r) is a “hard-to-print” difficulty filter that weights towards “hard-to-print” diffracted energy along the ith angular direction, and fMH(r) is an “easy-to-print” difficulty filter that weights towards “easy-to-print” diffracted energy along the ith angular direction, as further described below.
The (normalized) energy entropy factor Be,ij, is a measure of the energy entropy for the jth tile along the ith angular coordinate, and can be expressed as
Be,ij=∫0ipe,ij(e) log [pe,ij(e)]de, Eq. 4
where pe,ij(e) is a distribution function of energy values of the diffraction orders aj(ux, uy) along the ith angular direction θi.
The phase entropy factor, Bφ,ij, represents the distribution of phase φ of the diffraction orders aj(ux, uy) along the ith angular direction θi, and can be expressed as:
Bφ,ij=∫φ=02πpφ,ij(φ) log [pφ,ij(φ)]dφ. Eq. 5
where pφ,ij(φ) is a distribution function of phase values φ of the diffraction orders aj(ux, uy) of the jth tile along the ith angular direction θi.
The total energy entropy factor, ETj, represents the (normalized) total energy entropy of the diffraction orders aj(ux, uy) for tile j and can be expressed as:
ETj=∫e=01pej(e) log [pej(e)]de, Eq. 6
Where pej(e) is a distribution function of total energy entropy of the diffraction orders aj(ux, uy) of the jth tile.
In a preferred embodiment, a lithographic (or “litho”) difficulty metric LDij of the ith region for the jth tile is expressed as:
LDij=(WTj)α(Aij)[(B
where, for a given jth tile, WTj is the total energy of the diffracted orders which may be expressed as an integral over the unit circle:
WTj=∫r=01∫↓=02π|aj(r∠θ)|2rdrdθ, Eq. 8
Aij (see Eq. 3) is a energy ratio factor along the angular coordinate i, Be,ij (see Eq. 4) is a (normalized) energy entropy factor representing energy distribution of the diffracted orders along angular coordinate i, Bφ,ij (see Eq. 5) is a phase entropy factor representing distribution of phase φ the diffracted orders along angular coordinate i, ETj (see Eq. 6) is a total energy entropy factor representing total entropy of the diffracted orders, and α and β are experimentally determined constants which may be calibrated based on patterns having known difficulty characteristics. The inventors have found that the constant α may be typically in the range 0.1-0.3, and the constant β may be typically in the range of 0.002-0.01.
In accordance with the invention, the litho difficulty metric LDij is used to identify patterns or tiles that are binding patterns during an optimization of an entire chip layout, during an optimization procedure such as SMO. Binding patterns or tiles are those patterns or tiles that have active constraints during optimization of the chip layout.
One embodiment of a method in accordance with the invention, is illustrated in
Next, in Block 420, the diffraction orders aj(ux, uy) are computed for each of the unique tiles Pj(x, y), where aj(ux, uy) represents the Fourier transform, or equivalently, the diffraction order of the jth tile. Where multiple instances of the same jth tile Pj are repeated throughout the layout of the chip, only one instance of aj needs to be computed for a given layout. Methods for computing the diffraction orders in direction (or equivalently spatial frequency) space from a Cartesian description of the feature polygons are known in the art.
Next, in accordance with the invention, (Block 430) a lithographic difficulty energy ratio factor Aij (see Eq. 3) is computed for each jth tile along an angular coordinate θi. The lithographic difficulty energy ratio factor Aij is a representation of the relative amount of “hard-to-print” energy in the diffracted order aj of the jth tile.
In a preferred embodiment, the unit circle in spatial frequency space (r∠θ) is subdivided along the angular coordinate into Imax-radial regions Δθi, iε{1, 2, . . . , Imax}. For example, in
Δθ1={q:−45°<0≦45°}, Δθ2={q:45°<0≦135°}, Δθ3={q:135°<0≦225°}, Δθ4={q:225°<0≦315°}. The number of Imax regions may be any number suitable for the accuracy and computational cost desired for a given application.
The amplitude factor Wij(r) for the jth tile may then be computed for each ith radial region Δθi as
WΔθ
In accordance with Eq. 3 and Eq. 9 above, one embodiment of the energy ratio factor Aij may be computed for each region Δθi as:
where WΔθ
The design of the difficulty filters fIMH(r), fMH(r), may be better understood with reference to
The printability of more complex two-dimensional patterns is not easily classified based on a visual inspection of the patterns. More generally, relatively hard to print patterns will have higher order diffracted energy located in regions of the unit circle that are in a range ΔrH that is close to the edge of the unit circle r=1, as illustrated in
Thus, in accordance with the invention, an easy-to-print filter fMH(r) is provided to emphasize the higher order energy located in an intermediate range radial distances ΔrE in direction space that are associated with relatively easy-to-print patterns. One embodiment of an intermediate range easy-to-print filter fMH (r) 901 is illustrated in
Similarly, a hard-to-print filter fIMH(r) is provided to emphasize the higher order energy located in range of radial distances ΔrH in direction space that are associated with relatively hard-to-print patterns, i.e. having relatively high values of r. One embodiment of a hard-to-print filter fIMH(r) 902 is illustrated in
More generally, difficulty filters fIMH(r), fMH(r) may be designed to have any suitable shape, as illustrated in
Referring again to
Similarly, the entropy factors Be,ij, Bφ,ij, ETj are computed in this embodiment in accordance with the following equations (Block 440).
The energy entropy factor, Be,Δθ
Be,Δθ
Where pe,Δθ
The phase entropy factor representing phase distribution of the diffracted orders Bφ,Δθ
Bφ,Δθ
where pφ,Δθ
The factor ETj represents the total energy entropy of the diffracted orders aj(ux, uy) for tile j and can be computed in accordance with Eq. 6 above.
The distribution functions pe,ij(e), pφ,ij(φ) and pej(e) may be computed as a function of values of e and φ of the diffracted orders aj(ux, uy). For example, the range of values of e within a given region Δθi of the unit circle can be divided into M bins each containing values of e in the range Δem=em−em-1, mε{1, 2, . . . , M}, as illustrated in
Referring again to
LDj=max1≦i≦I
where i is an index referring to a region of the unit circle in direction space, and Imax is the number of regions that the unit circle is divided into. The constant hi is an empirically determined constant that can be used to take into account the relative importance of the region i, which may be due to the distribution of the illumination source in combination with the critical patterns to be printed.
For example, consider a portion 810 of a pattern of features to be printed as illustrated in
Referring again to
In another embodiment, a global litho difficulty metric for the jth tile may be expressed as:
{circumflex over (LDj)}=(WTj)α(Âj)[({circumflex over (B)}
where the total energy of the diffracted orders WTj may be obtained from Eq. 8, the total energy entropy factor ET may be obtained from Eq. 6, and Âj, {circumflex over (B)}ej and {circumflex over (B)}φj are defined below.
In this embodiment, the energy ratio factor Âj is expressed as follows:
Âj=max1≦i≦I
where i is an index referring to a region of the unit circle in direction space, and Imax is the number of regions that the unit circle is divided into. The constant ci is an empirically determined constant that can be used to take into account the relative importance of the region i, which may be due to the distribution of the illumination source.
In this embodiment, the entropy factors {circumflex over (B)}ej,{circumflex over (B)}φj may be determined from:
{circumflex over (B)}ej=max1≦i≦I
and
{circumflex over (B)}φj=max1≦i≦I
where di and gi are empirically determined constants that indicate the relative importance of each of the regions of the unit circle, based on the illumination source distribution.
Another embodiment is illustrated in
First, a set of K feasible chip layouts Sk, kε{1, 2, . . . , K} are provided (Block 1310). Typically, a basic set of JD unique design tiles Pj, jε{1, 2, . . . , JD} is available to the designer, according to a set of predetermined design rules, for use in creating a chip layout. Each of the k layouts Sk will include a subset JD(k) of the available of JD unique design tiles. For each layout Sk, the diffraction orders aj(k) are computed for each tile j(k), j(k)ε{1, 2, . . . , JD (k)} used in each of the k layouts Sk (Block 1320). Note that a particular tile Pj may be used in more than one layout, and if so, the diffraction order aj(k) for that tile only needs to be computed once for all the layouts that contain that tile.
The amplitude factors Wij(k)(r) and the energy ratio factors Aij(k) are computed for each unique j(k)th tile in each chip layout Sk (Block 1330). If these factors have previously been computed for the same tile in another of the K chip layouts, such computations need not be repeated.
The entropy factors Be,ij(k), Bφ,ij(k), ETj(k) are computed on each unique tile Pj(k) in each set Sk (Block 1340). If these factors have previously been computed for the same tile in another of the K chip layouts, such computations need not be repeated.
Then the lithographic difficulty metrics LDj(k) are computed for each unique tile Pj(k) in each layout Sk (Block 1350). The lithographic difficulty metric only needs to be computed once for each unique tile, and if it has been previously been computed for the same tile in another of the K chip layouts, such computations need not be repeated.
Next, for each layout Sk the value of the litho difficulty metrics LDj(k) are compared to a predetermined threshold difficulty value DTk for layout Sk (Block 1360). If, for all unique tiles j(k)ε{1, 2, . . . , J (k)}, within layout Sk, LDj(k)≦DTk, than the current kth layout is acceptable and the layout Sk may be output (Block 1390) and the next layout may be evaluated. In addition, the values of the litho difficulty metric LDj(k) may be output for all the unique J(k) tiles within layout Sk.
If, for any layout Sk, LDj(k)≦DTk, then not all of the tiles within the layout Sk have an acceptable litho difficulty value, and the current kth layout is deemed not acceptable. If the layout is not deemed to have acceptably small litho difficulty metric values, then the layout Sk is modified (Block 1370), for example, by replacing one or more tiles having unacceptably high litho difficulty values with other appropriate tiles, in accordance with the design rules. Then the energy ratio (Block 1330) and entropy factors (Block 1340) and litho difficulty metrics (Block 1350) are recomputed and evaluated until all the tiles within the layout Sk satisfy the litho difficulty threshold DTk for that layout (Block 1360). Although unlikely, if no acceptable modification of the layout Sk is found, for example, after a predetermined number of iterations, it may be necessary to reject that particular layout Sk, or add additional tiles to the available set of design rules.
Finally, the acceptable layout Sk may be used in further design processes (Block 1395), such as MBOPC, OPC Verification and/or SMO, with potential cost savings in optimization since the acceptable layouts will have been pre-designed to be relatively easy to print.
In one embodiment of the present invention, referring to
While the present invention has been particularly described, in conjunction with a specific preferred embodiment, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the present description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.
Number | Name | Date | Kind |
---|---|---|---|
6563566 | Rosenbluth et al. | May 2003 | B2 |
7069535 | Kobozeva et al. | Jun 2006 | B2 |
7254251 | Cai et al. | Aug 2007 | B2 |
7565633 | Mukherjee et al. | Jul 2009 | B2 |
7684013 | Hansen et al. | Mar 2010 | B2 |
7840917 | Bae et al. | Nov 2010 | B2 |
7981576 | Hsu et al. | Jul 2011 | B2 |
20030154460 | Taoka et al. | Aug 2003 | A1 |
20070094634 | Seizginer et al. | Apr 2007 | A1 |
20090217224 | Wiaux et al. | Aug 2009 | A1 |
20100131909 | Miloslavsky et al. | May 2010 | A1 |
20100151364 | Ye et al. | Jun 2010 | A1 |
Number | Date | Country |
---|---|---|
2009-092779 | Apr 2009 | JP |
Number | Date | Country | |
---|---|---|---|
20120017194 A1 | Jan 2012 | US |