The present invention relates to vertical trench MOSFETs, and more particularly, to a method of forming a thick bottom oxide in the trench of the MOSFET.
The vertical trench gated power MOSFET has rapidly displaced various forms of power MOSFETs due to performance and size improvements. For example, the vertical trench MOSFET can provide high density and current capability while having low on-state resistance and good off-state voltage blocking performance. In a trench MOSFET, current flows vertically through the substrate. A gate is formed within the trench of the substrate. The gate is typically formed from embedded polysilicon.
It is also known that a thick bottom oxide is desirable at the bottom of the trench in order to improve the gate breakdown voltage. Also, having a thick bottom oxide lowers the gate to drain capacitance. Examples of prior art methods of forming a thick bottom oxide in a vertical trench MOSFET can be seen in U.S. Patent Publication No. 2007/0202650 entitled “Low Voltage Power MOSFET Device and Process for Its Manufacturer.” In that disclosure, a silicon dioxide layer is grown on the exposed silicon at the bottom of the trench. This growth is typically performed using thermal oxidation. However, a drawback of such a technique is that thermal oxidation increases the thermal budget required in the process.
Another method of forming the thick bottom oxide is disclosed in U.S. Patent Publication No. 2005/0236665 entitled “Trench MIS Device Having Implanted Drain/Drift Region and Thick Bottom Oxide and Process for Manufacturing the Same.” As disclosed in that publication, the thick bottom oxide layer is formed on the bottom of the trench while sidewall spacers are still in place. In that disclosure, the thick bottom oxide can be formed by thermal growth or by conventional chemical vapor deposition. However, this method again increases the thermal budget, and/or is unsuitable for high aspect ratio trench MOSFETs.
A method for forming a thick bottom oxide in the bottom of a trench used in a vertical MOSFET. Initially, an n-type substrate has an n-type epitaxial layer grown thereon. A top portion of the n-type epitaxial layer is implanted with p-type dopants to provide a p-layer. A trench is then etched into the p- and n-type epitaxial layer. A high density plasma chemical vapor deposition (HDPCVD) process is used to either partially or fully fill the trench. Any oxide on the top surface of the p-layer is then removed, such as by using a chemical mechanical polishing step. Then, an isotropic etching step, such as a wet etch, is used to remove the silicon dioxide from the trench, while leaving a thick bottom oxide at the bottom of the trench. The HDPCVD process utilizes minimal thermal budget to form the thick bottom oxide. Next, a thin gate oxide is formed on the side walls of the trench using a thermal oxidation step. After the gate oxide layer is formed, conventional steps are used to finish the vertical MOSFET, including formation of a polysilicon gate within the trench and n+ doping on the regions adjacent the trench to form the source regions of the MOSFET.
Specifically, turning to
Additionally, although the substrate is an n+ substrate and the epitaxial layer is n-type with a p-type implanted layer, the types of the semiconductor layers can be reversed, thus forming a pnp type transistor instead of an npn type transistor. Finally, it should be noted that, for clarity, the particular aspect ratio of the trench 201 is depicted as being relatively low in the Figures compared to typical applications. In other words, the ratio of the depth of the trench 201 to the width of the trench 201 is shown in the Figures to be on the order of 1 to 1.5. However, in most applications, the aspect ratio will be higher than that, and typically greater than 2.
In an alternative embodiment, the trench 201 is formed prior to formation of the p-type layer 105. Thus, the trench 201 is formed after the n-type epitaxial layer 103 is formed on the substrate. This can be seen best in
For example, the trench 201 may be etched using either a hard mask or a soft mask. In one embodiment, the hard mask is formed prior to the trench etching. As seen in
After the trench has been formed, next, turning to
The HDPCVD process is a combination of deposition and sputtering. By controlling the deposition to sputter ratio, various aspect ratios of the trench 201 can be easily filled. In general, and without being limiting, the higher the aspect ratio of the trench 201, the higher the deposition to sputter ratio required in the HDPCVD process. In one embodiment, the deposition to sputter (D/S) ratio is greater than 4.
Once the oxide layer 301 has been formed into the trench 201, further processing steps are then required. At this point, it should be noted that the trench 201 need not be completely filled by the oxide 301. Indeed, as shown in
In any event, the oxide 301 that lies outside of the trench 201 should be removed. This can be done using, for example, a chemical mechanical polishing step that stops on the top surface of the p-layer. Alternatively, an isotropic wet etch or a anisotropic dry etch may be used to remove portions of oxide 301 outside of the trench 201. However, this may result in portions of the oxide within the trench 201 being removed as well. As will be seen below, this may also be advantageous if the oxide 301 on the sidewalls f the trench are fully or partially removed in this step.
If a chemical mechanical polishing step is used, the remaining oxide 301 within the trench 201 is thus an oxide plug. Again, depending upon the quality of the CMP process, it may be difficult to stop the CMP process at the p-silicon surface. Thus, in an alternative embodiment, as noted above, prior to the deposition of the oxide 301, a thin silicon nitride layer, a silicon oxide layer, or an ONO layer may be deposited over the p-layer 105. This will provide a hard stop to the CMP process and advantageously provides greater control during the CMP process. While what has been described as a CMP process taking place after the oxide deposition, in an alternative embodiment, the CMP process may take place after the polysilicon gate plug is formed within the trench.
Next, turning to
Next, turning to
The remaining steps to form the MOSFET are conventional trench MOSFET processes and will not be detailed here in order to avoid obscuring the invention. However, briefly, a polysilicon plug 801 is formed in the trench 201 as seen in
Note that in the alternative embodiment described in
From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.