Claims
- 1. A method of forming an integrated circuit including a highly resistive amorphous silicon resistor, comprising the steps of:
- forming a first conductive layer over a substrate;
- removing portions of said first conductive layer to form a first plate of a capacitor;
- forming a dielectric layer over said first conductive layer;
- forming an amorphous silicon layer over said dielectric layer;
- removing portions of said amorphous silicon layer to define a second amorphous silicon plate of said capacitor and the body of a highly resistive amorphous silicon resistor;
- forming an insulator layer over a first portion of said highly resistive amorphous silicon resistor; and
- forming contacts in contact with second and third portions of said highly resistive amorphous silicon resistor.
- 2. The method of claim 1 wherein said step of removing portions of said amorphous silicon layer further includes defining a fuse.
- 3. The method of claim 1 and further comprising the steps of:
- masking portions of said resistor body; and
- doping said second amorphous silicon plate of said capacitor and the unmasked portions of said resistor body.
- 4. The method of claim 2 and further comprising the steps of:
- masking portions of said fuse; and
- doping said second amorphous silicon plate and the unmasked portions of said fuse.
- 5. The method of claim 4 wherein said doping step comprises doping said second amorphous silicon plate and the unmasked portions of said fuse with a dopant of a first conductivity type and further comprising the step of:
- masking said fuse and said amorphous silicon second plate; and
- doping said resistor body with a dopant of a second conductivity type.
- 6. The method of claim 1 and further comprising the step of forming a mask over a portion of said substrate in which a diode is formed.
- 7. The method of claim 6 and further comprising the steps of siliciding portions of the resistor and said second amorphous silicon plate, the mask over said substrate operable to prevent silicidation over said diode portion of said substrate.
- 8. The method of claim 1 wherein said step of removing portions of said first conductive layer further includes the step of defining gates for one or more MOS transistors and polysilicon emitters for one or more bipolar transistors.
- 9. The method of claim 3 wherein said doping step further comprises doping source/drain regions for an MOS transistor.
- 10. The method of claim 9 wherein said doping step further comprises doping a collector region for a bipolar transistor.
Parent Case Info
This application is a Continuation of application Ser. No. 018,354, filed Feb. 16, 1993, now abandoned, which is a Continuation of application Ser. No. 07/738,029, filed Jul. 30, 1991, now abandoned, which is a division of application Ser. No. 07/375,080, filed Jun. 30, 1989, now U.S. Pat. No. 5,047,826.
US Referenced Citations (16)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0171230 |
Jul 1989 |
JPX |
Divisions (1)
|
Number |
Date |
Country |
Parent |
375080 |
Jun 1989 |
|
Continuations (2)
|
Number |
Date |
Country |
Parent |
18354 |
Feb 1993 |
|
Parent |
738029 |
Jul 1991 |
|