The present disclosure relates generally to semiconductor devices and, more particularly, to a method for forming metal lines in a semiconductor device.
In general, as semiconductor devices become more highly integrated, the importance of metal lines increases. Specifically, in a logic design technique as well as a memory design technique, the use of a back end of line (“BEOL”) process becomes greater than that of a front end of line (“FEOL”) process. This trend has caused a decrease in the operating speeds of semiconductor devices due to increases in resistance and parasitic capacitance upon formation of the metal lines.
For example, U.S. Pat. No. 6,448,649 discloses a method of forming plugs of two layers by deposition of a material for the plugs into holes and U.S. Pat. No. 6,130,102 discloses a method of forming plug of a dual damascene type to prevent a leakage current in a capacitor. However, such conventional methods cause structural problems and result in a high manufacturing cost of the semiconductor device.
As described in greater detail below, an example method for forming metal lines in a semiconductor device, includes forming first metal lines and a first insulation layer on the first metal lines, etching the first insulation layer until the first metal lines are exposed, depositing a conductive material into the etched portion of the first insulation layer to form contact plugs, forming a second insulation layer on the resultant structure, etching the second insulation layer to expose the contact plugs, depositing a material for cores into the etched portions of the second insulation layer to form the cores. In addition, the example method may further include selectively removing the second insulation layer to expose the cores, and depositing a second metal lines on both sides of the cores to branch current to both sides of the cores.
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With the example apparatus and methods described herein, an electromigration (“EM”) characteristic of the metal lines is improved and a manufacturing cost of the semiconductor device is decreased.
Although certain methods and apparatus have been described herein, the scope of coverage of this patent is not limited thereto. To the contrary, this patent covers all embodiments fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.
Number | Date | Country | Kind |
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10-2002-0086401 | Dec 2002 | KR | national |
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5981377 | Koyama | Nov 1999 | A |
6130102 | White, Jr. et al. | Oct 2000 | A |
6159820 | Park | Dec 2000 | A |
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Number | Date | Country | |
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20040219776 A1 | Nov 2004 | US |