Claims
- 1. A method for making a diode formed in a polycrystalline silicon layer, which comprises the steps of:
- forming a pattern of a polycrystalline silicon layer either of an intrinsic semiconductor layer or a layer including impurities at a low concentration therein, on a substrate;
- increasing a carrier mobility in said polycrystalline silicon layer;
- forming first, second and third regions by introducing P-type and N-type impurities into said second and third spaced areas in said polycrystalline silicon layer, respectively, at high concentration, to form said second and third regions with the first region having a predetermined width W in said polycrystalline silicon layer, therebetween;
- setting said width to follow a relation WD<W<L where L represents a carrier diffusion length and WD represents a width of the depletion layer in the polycrystalline silicon when a breakdown voltage is applied thereto; and
- forming electrodes electrically connected to said second and said third regions.
- 2. A method for making a diode formed in a polycrystalline silicon layer according to claim 1, wherein said step of increasing carrier mobility is a step for enlarging a grain size of said polycrystalline silicon layer.
- 3. A method for making a diode formed in a polycrystalline silicon layer according to claim 1, wherein said step of forming the pattern of said polycrystalline silicon layer is a step of forming the polycrystalline silicon layer in such a manner that said concentration thereof is set at 1.times.10.sup.18 cm.sup.-3 or less, and said step of introducing P-type and N-type impurities into said regions is a step of introducing said impurities into said second and said third regions in such a manner that said concentration of the impurities thereof is set at 1.times.10.sup.20 cm.sup.-3 .about.1.times.10.sup.21 cm.sup.-3.
- 4. A method for making a diode formed in a polycrystalline silicon layer according to claim 2, wherein said step of forming the pattern of said polycrystalline silicon layer is a step of forming the polycrystalline silicon layer in such a manner that said concentration thereof is set out at 1.times.10.sup.18 cm.sup.-3, or less and said step of introducing P-type and N-type impurities into said regions is a step of introducing said impurities into said second and said third regions in such a manner that said concentration of the impurities thereof is set at 1.times.10.sup.20 cm.sup.-3 .about.1.times.10.sup.21 cm.sup.-3.
- 5. A method for making a diode formed in a polycrystalline silicon layer according to claim 4, wherein said step of introducing said P-type and N-type impurities into said regions is a step of introducing said impurities into said regions by the ion implanting method in the form of a self-alignment utilizing a rectangular shaped layer formed on said first region as a mask.
- 6. A method for making a diode formed in a polycrystalline silicon layer according to claim 5, wherein said step of introducing said P-type impurities into said region is a step of introducing said impurities into said region by the ion implanting method in the form of a self-alignment utilizing a rectangular shaped polycrystalline silicon layer formed on said first region with an insulating film therebetween as a mask and said polycrystalline silicon layer used as said mask being formed simultaneously with forming an electrode formed on the same substrate.
- 7. A method for making a diode formed in a polycrystalline silicon layer, which comprises the steps of;
- forming a pattern of a polycrystalline silicon layer including impurities at a low concentration therein, on a substrate as a first region;
- forming first, second and third regions, said second and third regions oppositely arranged from each other with said first region therebetween;
- defining a predetermined width W of said first region in said polycrystalline silicon layer, said predetermined width W of said first region being defined so as to fulfill the following equation: ##EQU6## wherein, K s represents the dielectric constant of silicon, .epsilon..sub.O represents the dielectric constant in a vacuum, q represents the elementary electric charge, N.sub.A represents the concentration of the impurities in the first region, V represents required break down voltage for the diode, K represents Boltzmann's constant, T represents the absolute temperature, t represents the carrier mobility, n.sub.i represents the intrinsic carrier concentration, W b denotes the width of the depletion layer when the predetermined voltage is applied thereto and Js represents the generation current density generated when the predetermined voltage is applied thereto;
- introducing P-type and N-type impurities into said second and third regions in said polycrystalline silicon layer, respectively, at high concentration; and
- forming electrodes electrically connected to said second and said third regions.
- 8. A method for making a diode formed in a polycrystalline silicon layer according to claim 7, wherein said method further comprises the steps of increasing a carrier mobility in said polycrystalline silicon layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
63-38418 |
Feb 1988 |
JPX |
|
Parent Case Info
This is a division of application No. 07/734,099, filed Jul. 23, 1991, abandoned, which is a continuation of application No. 07/312,658 filed Feb. 21, 1989, abandoned.
US Referenced Citations (7)
Foreign Referenced Citations (3)
Number |
Date |
Country |
57-141962 |
Sep 1982 |
JPX |
58-151051 |
Sep 1983 |
JPX |
61-134079 |
Jun 1986 |
JPX |
Non-Patent Literature Citations (1)
Entry |
Gerzberg et al., IEEE Electron Device Letters, "A Quantitative Model of the Effect of Grain Size on the Resistivity of Polycrystalline Silicon Resistors", Mar. 1980, vol. EDL-1, No. 3. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
734099 |
Jul 1991 |
|
Continuations (1)
|
Number |
Date |
Country |
Parent |
312658 |
Feb 1989 |
|