Claims
- 1. A method for making a semiconductor device from a wafer including a silicon epitaxial surface layer, said method comprising the steps of heating the wafer in an oxidizing atmosphere for a time and at a temperature for forming a first SiO.sub.2 overlay, forming a first layer of doped polysilicon over said SiO.sub.2 layer, depositing on said polysilicon layer a second layer of a material selected from the group consisting of Ti and Ta sintering the material of said second layer at a temperature and for a time to form a silicide TiSi.sub.2 and TaSi.sub.2 of the material, respectively, heating the wafer for a time and at a temperature to form a second SiO.sub.2 overlay while leaving a layer of polysilicon in excess of 1000 Angstroms therebeneath, etching a pattern in said second SiO.sub.2 overlay, depositing an electrically-conducting material over said second SiO.sub.2 overlay, and etching a pattern in said electrically-conducting material.
- 2. A method in accordance with claim 1 in which said second layer comprises Ti and is sintered at about 900 degrees C. and heated in an oxygen atmosphere.
- 3. A method in accordance with claim 1 in which said second layer comprises Ta and is sintered at at least about 1000 degrees C. and is heated in steam.
Parent Case Info
This application is a division of application Ser. No. 974,378, filed Dec. 24, 1978, now U.S. Pat. No. 4,276,557.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
4128670 |
Gaensslen |
Dec 1978 |
|
4180596 |
Crowder et al. |
Dec 1979 |
|
Non-Patent Literature Citations (1)
Entry |
Sinha et al., "Generic Reliability of the High-Conductivity TaSi.sub.2 /n+ Poly-Si Gate MOS Structure", 18th Annual Proceedings Reliability Physics 1980, Las Vegas, Nevada, Apr. 8-10, 1980. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
974378 |
Dec 1978 |
|