Patent Application
20220201852
The invention relates to the field of integrated circuits and packaging, and to a method for manufacturing a multilayer circuit structure, and the structure made thereby.
As the trend of the consumer electronic and communication products is toward lighter, thinner, and higher efficiency, the circuit substrate used on a main board of the electronic products requires to have higher layout density. In the electronics products, the circuit substrate, e.g., a printed circuit board (PCB) for packaging integrated circuits (IC or chips) also plays an important role. As the contact number and the contact density of a chip increase, the contact number and the contact density of a circuit substrate for packaging chips increase correspondingly. Therefore, the requirement of circuit substrates with higher layout density is a continuous need.
Currently, the method for stacking a plurality of patterned conductive layers and a plurality of dielectric layers on a circuit substrate includes a laminating process and a build-up process. These processes include laminating the dielectric layers on the surface of patterned circuit layers; then a plated through hole (PTH) or a via serves as the channel for connecting the patterned conductive layers residing on the different dielectric layers.
U.S. Pat. No. 9,237,643 B2 discloses a conventional fabrication process for a circuit board having an embedded circuit on one side. The fabrication process includes: i) providing a core panel having dielectric layers on both outer surfaces, ii) forming fine circuit grooves (i.e. trenches) and at least one through hole or via by laser ablating on one outer surface; iii) filling the fine circuit grooves and through hole and/or via with conductive material by electroplating; iv) removing the excess conductive material, for example, by grinding to form an embedded fine circuit pattern on one surface of the core panel. The other surface of the core panel now covered with un-patterned conductive layer may be further processed to form patterned conductive layer by a subtractive process, additive process, or a semi-additive process. Finally, a patterned solder mask may be formed on each outer surface to complete the fabrication of a circuit board structure.
U.S. Pat. No. 8,164,004 B2 discloses a similar fabrication process for a circuit board having embedded circuits 11a and 11b on both sides of a core panel 10 (see
According to the aforesaid fabrication processes, the circuit pattern is formed in the dielectric material by laser ablating on one or both surfaces of a core panel. One of the drawbacks of the laser ablation process is that the process is slow, thus low through-put and leads into increased production cost. Another concern is that the circuits 11a and 11b formed by laser ablating has a trench profile of a trapezoid with slanted sidewalls versus a desired rectangular with vertical sidewalls (see
The present invention is directed to a method for manufacturing a multilayer circuit structure having embedded trace layers and the multilayer circuit structure made thereby.
According to the first aspect of the present invention is to provide a method for manufacturing a multilayer circuit structure, comprising:
In an embodiment, the method of the present invention, wherein the step (iv) patterning each metal layer by photoimaging, comprises:
According to the second aspect of the present invention is to provide a multilayer circuit structure manufactured by the present method, comprising:
wherein
Various other features, aspects, and advantages of the present invention will become more apparent with reference to the following Figures, description, examples, and appended claims. The following figures are included for better understanding of the invention and are incorporated in and constitute a part of this specification.
All publications, patent applications, patents and other references mentioned herein, if not otherwise indicated, are explicitly incorporated by reference herein in their entirety for all purposes as if fully set forth.
Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. In case of conflict, the present specification, including definitions, will control.
Unless stated otherwise, all percentages, parts, ratios, etc., are by weight.
As used herein, the term “produced from” is synonymous to “comprising”. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, process, method, article, or apparatus.
The transitional phrase “consisting of” excludes any element, step, or ingredient not specified. If in the claim, such a phrase would close the claim to the inclusion of materials other than those recited except for impurities ordinarily associated therewith. When the phrase “consisting of” appears in a clause of the body of a claim, rather than immediately following the preamble, it limits only the element set forth in that clause; other elements are not excluded from the claim as a whole.
The transitional phrase “consisting essentially of” is used to define a composition, method or apparatus that includes materials, steps, features, components, or elements, in addition to those literally discussed, provided that these additional materials, steps features, components, or elements do not materially affect the basic and novel characteristic(s) of the claimed invention. The term “consisting essentially of” occupies a middle ground between “comprising” and “consisting of”.
The term “comprising” is intended to include embodiments encompassed by the terms “consisting essentially of” and “consisting of”. Similarly, the term “consisting essentially of” is intended to include embodiments encompassed by the term “consisting of”.
When an amount, concentration, or other value or parameter is given as either a range, preferred range or a list of upper preferable values and lower preferable values, this is to be understood as specifically disclosing all ranges formed from any pair of any upper range limit or preferred value and any lower range limit or preferred value, regardless of whether ranges are separately disclosed. For example, when a range of “1 to 5” is recited, the recited range should be construed as including ranges “1 to 4”, “1 to 3”, “1-2”, “1-2 & 4-5”, “1-3 & 5”, and the like. Where a range of numerical values is recited herein, unless otherwise stated, the range is intended to include the endpoints thereof, and all integers and fractions within the range.
When the term “about” is used in describing a value or an end-point of a range, the disclosure should be understood to include the specific value or end-point referred to.
Further, unless expressly stated to the contrary, “or” refers to an inclusive “or” and not to an exclusive “or”. For example, a condition A “or” B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present).
Embodiments of the present invention as described in the Summary of the Invention include any other embodiments described herein, can be combined in any manner.
The invention is described in detail herein under.
In the first embodiment of the present invention, a method for manufacturing a multilayer circuit structure with double-side conductive layers is described.
Referring to
In one embodiment, the substrate has a thickness ranging from about 40 μm to about 800 μm, and is derived from a copper clad laminate that has a base sheet composed of a reinforced resin or a resin coated copper (RCC) foil, and the resin is selected from epoxy resin, phenolic resin, bismaleimide-triazine (BT) resin, polyimide (PI), cyanate ester resin (CE), polyphenylene oxide (PPE), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), or mixtures thereof. Referring to
In one embodiment, the thermally curable polymer is selected from the group consisting of epoxy resin, bismaleimide-triazine (BT) resin, polyimide (PI), cyanate ester resin (CE), polyphenylene oxide (PPE), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), and mixtures thereof.
In another embodiment, the dielectric layer further comprises a reinforcing material or a plurality of fillers.
In yet another embodiment, the reinforcing material is in form of fibers or a fabric, and comprises E-glass, S-glass, quartz, ceramic, or aramid.
In a further embodiment, the plurality of fillers are particles composed of silicon oxide, aluminum oxide, boron nitride, or mixtures thereof; and have an average diameter ranging from about 1 μm to about 20 μm.
Referring to
In one embodiment, the metal layer is formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroless-plating. Noted that in the PCB fabrication industry the PVD method is also referred as “sputtering.”
In one embodiment, the metal layer is composed of Cu, Ni, Ti, W, Al, Cr, Co, Ag, Au, Pd, and alloy thereof. In another embodiment, the metal layer is composed of Cu and Cu alloy. Referring to
According to the present method, the photoimaging process comprises:
Referring to
Noted that the metal mask may be removed before or after the via formation step (vii). Alternatively, provided that the metallic material of the metal mask is the same as the conductive metal is used in the step (viii), it may not be removed at all.
Referring to
Depending on the application of the multilayer circuit structure, the step (vii) of forming at least one via may be done by plasma etching to provide a via profile with vertical sidewalls to minimize the signal loss.
Referring to
The method for depositing the conductive metal may include pre-forming a seed layer and followed by electrolytic plating. Suitable method for forming the seed layer includes, but not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroless plating.
When trace pattern of the dielectric layer contains trenches and vias with a broad range of widths and diameters, to obtain a conductive metal layer 140 with uniform thickness becomes a challenge by a single plating process. Especially, when multiple trenches (including the ground area) and vias of the trace pattern have a width and diameter being greater than 150 μm.
One aspect of the invention is to provide a dual plating method to solve the abovementioned problem.
In one embodiment, the electrolytic plating includes a single plating method or a dual plating method.
The dual plating method of the present invention may comprise steps I-IV as follows:
Alternatively, the dual plating method of the present invention may comprise steps A-D as follows:
Referring to
In one embodiment, the planarization method includes etching, mechanical grinding, or chemical mechanical polishing (CMP).
In another embodiment, the planarization method includes electrolytic thinning, flash etching, surface ablation/plasma cleaning, or other related techniques.
Referring to
Noted that steps (ii)-(ix) of the present method may be repeated multiple times as needed to provide a multilayer circuit structure.
In the second embodiment of the present invention, a method for manufacturing a multilayer circuit structure with double-side conductive layers is described.
Referring to
In one embodiment, the through hole is a hollow cylinder with a layer of metallic material composed of Cu or Cu alloy with a layer thickness of about 15 μm to about 25 μm.
In another embodiment, the through hole coated with a layer of metallic material is then filled with an organic polymer composed of epoxy resin or phenolic resin.
Referring to
Noted that since the through hole 212 has been filled with an organic polymer 216, the thermally curable polymers for forming the dielectric layers 222 and 224 may be the same or different.
In one embodiment, the thermally curable polymers for forming the dielectric layers 222 and 224 are the same.
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As described previously, suitable planarization method includes etching, mechanical grinding, or chemical mechanical polishing (CMP).
In the third embodiment of the present invention, a method for manufacturing a multilayer circuit structure with double-side conductive layers is described.
Referring to
Referring to
Noted that since the through hole 312 has been filled with a metallic material, the single-side metal clad 320a or 320b may be the same or different. Generally, the single-side metal clad 320a or 320b has a thickness of about 10 μm to about 50 μm. The metal foil of said single-side metal clad is composed of Cu, Ni, Ti, W, Al, Cr, Co, Ag, Au, Pd, and alloy thereof; and has a thickness ranging from about 3 μm to about 15 μm.
In one embodiment, the single-side metal clads 320a or 320b are the same.
In another embodiment, the metal foil of single-side metal clad is composed of Cu or Cu alloy.
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In the fourth embodiment of the present invention, a method for manufacturing a multilayer circuit structure with a conductive layer and IC chip inside is described.
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In the fifth embodiment of the present invention, a method for manufacturing a multilayer circuit structure with double-side conductive layers is described.
Referring to
The dielectric layers 520 and 521 have indent patterns embedded therein. Each indent pattern includes multiple narrow trenches (522 or 523, i.e. trenches have a width no more than 150 μm), wide trenches (524 or 525, i.e. trenches have a width greater than 150 μm), and vias (526 or 527, with a diameter ranging from about 20 μm to about 250 μm).
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In the following example for manufacturing the multilayer circuit structure according to present method are described in detail.
Step 1. Forming a Dielectric Layer
A single-side PCB (a coupon size: 50 mm×150 mm) was used as the substrate. Said substrate had an existing circuit with traces and pads. A dielectric film (manufactured by Ajinomoto Build Film, model GX-92R, 60 μm in thickness) was laminated on the substrate under vacuumed, at 90° C. with a pressure of 0.7 MPa for 60 sec, and then flatten at 90° C. with a pressure of 1.0 MPa for 60 sec.
Step 2. Forming a Metal Layer
A copper layer was deposited on the dielectric layer of the substrate obtained from Step 1, by sputtering copper with a PVD coating machine (manufactured by UVAT Technology Co., model: UHSD-060302T). The fiducial concentration was Copper 4N to form a Cu layer of 0.2 μm in thickness.
Step 3. Forming a Metal Hard Mask
A photoresist layer was formed by laminating a dry film (Riston® TH1015, 15 μm in thickness, manufactured by DuPont Electronics, Inc.) on the copper layer of the substrate obtained from Step 2. A roll laminator was used and the lamination was done at 100° C. with a pressure of 1.4 MPa and a rolling speed of 1.0 meter/minute.
The photoresist pattern was created by using ADTEC IP-8 with a wavelength of 405 nm, by SST=18/41. The test pattern with a conventional design by the PCB fabricator was used, which included line/space set at 20 μm/20 μm, wider trenches up to 60 μm, pads of 120 μm, and a ground area >2000 μm. After completion of the exposure, the uncured part of the photoresist layer was stripped and removed by treatment of a 2% Na2CO3 solution for 3 minutes, rinsed with DI water, and dried.
The unmasked copper areas were etched away, using a sodium persulfate (Na2S2O8) solution (130 g/L) at a conventional horizontal line with 1 m/min speed until completion, rinsed with DI water, and dried.
The photoresist pattern was then stripped and removed by treatment of a 10% NaOH solution for 90 seconds. After rinsing and drying, a copper hard mask was formed on the substrate.
Step 4. Patterning the Dielectric Layer
After forming the hard mask, the exposed areas of the dielectric layer were removed by plasma etching, using an inductively coupled plasma reactive ion etching (ICP-RIE) system (manufactured by Schmid Group), and the process gas was a mixture of CF4, O2, and N2 for reacting 20 min to form an indent pattern on the dielectric layer with an etching depth of 15 μm.
Step 5. Metal Hard Mask Removal
The copper hard mask was removed, using a sodium persulfate solution (130 g/L) at a conventional horizontal line with 1 m/min speed until completion, rinsed with DI water, and dried.
Step 6. Via Formation
In order to make circuit connection between the existing conductor and the circuit to be made in subsequent steps, ca. 250 vias with a diameter of 75 μm were made by laser drilling to reach the conductor/pad underneath, using a Mitsubishi Laser Drill, model: GTW5, with a CO2 laser.
Step 7. Depositing Conductive Metal
A seed layer was formed by sputtering Ti, then Cu, using a PVD coating machine (manufactured by UVAT Technology Co., model: UHSD-060302T). The fiducial concentrations were titanium 2N7 and copper 4N. The resulting Ti layer had a thickness 0.1 μm and the Cu layer had a thickness of 0.2 μm.
After forming the seed layer, the first electroplating was conducted in a 20 L paddle plater, with a plating solution (MICROFILL™ AET-1, available from DuPont Electronics, Inc.) and a current density of 2.0 ASD for 31 minutes to obtain a plating thickness of about 12 μm. The fine lines of the indent pattern, i.e. those trenches have a width of 20 μm to 150 μm were filled completely.
A photoresist layer was formed on the substrate after the first electroplating by laminating a dry film (Riston® TH1015, 15 μm in thickness). A roll laminator was used and the lamination was done at 100° C. with a pressure of 1.4 MPa and a rolling speed of 1.0 meter/minute.
The photoresist pattern was created by using ADTEC IP-8 with a wavelength of 405 nm, by SST=18/41. A pattern that would cover the copper-filled fine lines was used. After completion of the exposure, the uncured part of the photoresist layer was removed by treatment of a 2% Na2CO3 solution for 3 minutes, rinsed with DI water, and dried.
After forming the resist pattern, the second electroplating was conducted in a 20 L paddle plater, with a plating solution (DuPont MICROFILL™ AET-1) and a current density of 2.0 ASD for 20 minutes to obtain a plating thickness of about 8 μm. All the trenches/vias/ground area of the indent pattern of the dielectric layer was filled with copper.
The photoresist pattern was then removed by treatment of a 10% NaOH solution for 90 seconds. After rinsing and drying, a copper hard mask was formed on the substrate.
Step 8. Planarization
The substrate after dual plating process was planarized by a chemical mechanical polishing (CMP) with a pad (manufactured by DuPont, Suba™ 600) and a slurry (RDS MK10-001). The operation parameters were as follows: a pad/holder speed of 223/211, a down force of 3 psi, process time of 120 seconds, and a slurry flow rate of 80 mL/min.
After rising and drying, the substrate with a new embedded circuit was obtained, i.e. an embodiment of the present multilayer circuit structure. The multilayer circuit structure manufactured by the present method was then evaluated with a cross-section analysis with a microscope.
While the invention has been illustrated and described in typical embodiments, it is not intended to be limited to the details shown, since various modifications and substitutions are possible without departing from the spirit of the present invention. As such, modifications and equivalents of the invention herein disclosed may occur to persons skilled in the art using no more than routine experimentation, and all such modifications and equivalents are believed to be within the spirit and scope of the invention as defined by the following claims.
| Number | Date | Country | |
|---|---|---|---|
| 63127544 | Dec 2020 | US |
