Patent Application
20070094871
This application claims the benefit of Korean Patent Application No. 2005-104674 filed on Nov. 3, 2005 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method for manufacturing a printed circuit board with a film capacitor embedded therein and a printed circuit board obtained thereby. More particularly, the present invention relates to a printed circuit board with a film capacitor embedded therein in which a metal seed layer of the film capacitor is formed by electroless plating to reduce manufacturing costs and the film capacitor can be effectively embedded in an organic board by a build-up process, and a printed circuit board obtained thereby.
2. Description of the Related Art
Recently, there has been a rising demand for highly integrated passive devices to ensure higher performance of electronic devices. Nonetheless, a general perception is that various assortments of passive devices mounted on a printed circuit board significantly hinder downscaling of the electronic devices. Especially, semiconductor active devices are equipped with an increasing number of input and output terminals. This requires more passive devices to be mounted around the active devices but such spatial availability is not easily attainable.
The passive device is represented by a capacitor, which needs to be suitably positioned to reduce inductance resulting from a higher frequency trend. For example, a decoupling capacitor for stably supplying a power voltage is necessarily disposed in the closest proximity to an input terminal to diminish inductance resulting from the higher frequency trend.
To meet a demand for miniaturization and higher frequency trend, various types of laminated capacitors with low equivalent series inductance (ESL) have been developed. However a conventional multilayer chip capacitor (MLCC) faces a fundamental limitation in overcoming the problem just described. Meanwhile the capacitor is chiefly used as a device for an electrical circuit. Thus an electrical circuit board having the capacitor embedded therein can be decreased in its size. With this notion, recently a method for manufacturing an embedded capacitor has been vigorously studied.
The embedded capacitor is incorporated in a printed circuit board which is employed in memory cards, PC main boards and all kinds of RF modules, thereby dramatically downsizing the product. Also, the embedded capacitor is disposed in the close proximity to the input terminal of the active device, thereby minimizing electrical lines and remarkably lowering inductance.
This embedded capacitor is disclosed in U.S. Pat. No. 6,818,469. As shown in
In manufacturing the conventional film capacitor, the upper and lower electrodes are formed by physical vapor deposition (PVD) such as sputtering and E-beam. Disadvantageously this causes the electrodes to be formed to a desired thickness at considerable costs. Therefore, this conventional process is hardly applicable to a general build-up process without accompanying realistic limitations.
Furthermore, the aforesaid process involves heating the dielectric thin film at a temperature of at least 400° C. to enhance dielectric properties thereof. Therefore, this process can not be employed in manufacturing the printed circuit board, which is a polymer composite-based insulating substrate.
The present invention has been made to solve the foregoing problems of the prior art and it is therefore an object according to certain embodiments of the present invention is to provide a method for manufacturing a dielectric printed circuit board with a film capacitor embedded therein by low temperature film formation at lower costs.
Another object according to certain embodiments of the invention is to provide a printed circuit board manufactured by the method just described.
According to an aspect of the invention for realizing the object, there is provided a method for manufacturing a printed circuit board with a film capacitor embedded therein, the method comprising steps of:
forming a lower electrode on an insulating substrate; forming an amorphous dielectric film on the lower electrode by low temperature film formation;
According to another aspect of the invention for realizing the object, there is provided a printed circuit board with a film capacitor embedded therein, which is manufactured by the method just described.
The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
a to 2f are cross-sectional views illustrating a method for manufacturing a printed circuit board with a film capacitor embedded therein according to an embodiment of the invention;
FIG.3 is a cross-sectional view illustrating an embedded film capacitor manufactured according to another embodiment of the invention; and
Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
Preferably, the lower electrode 23 is formed on the insulating substrate 21a by conducting electrolytic plating after electroless plating. Here, preferably, the lower electrode 23 is formed to a thickness up to 2.0 μm. More preferably, in the lower electrode 23, a portion formed by electroless plating 23a and a portion formed by electrolytic plating 23b each have a thickness up to 1.0 μm.
Moreover, according to the invention, the lower electrode 23 is preferably made of one selected from a group consisting of Cu, Ni, Al, Pt, Ta and Ag. More preferably, the lower electrode 23 is made of Cu.
Meanwhile, the insulating substrate 21a and 21b is made of polyimid or epoxy, which is typically used to manufacture a printed circuit board.
Then as shown in
Preferably, the amorphous dielectric film 25 is made of a BiZnNb-based amorphous metal oxide and more preferably a metal oxide having a composition expressed by BixZnyNbzO7 where 1.3<x<2.0, 0.8<y<1.5, and z<1.6. The dielectric film composed of this amorphous oxide may exhibit a high dielectric constant of at least 30, or further at least 40 through low temperature thermal treatment.
Alternatively, the dielectric film 25 is preferably made of one selected from a group consisting of Bix(M′yMz″)O7 oxides satisfying relationships of 1.3<x<2.0, 0.8<y<1.5, and z<1.6 (here M′ is one selected from a group consisting of Zn, Mg, Ni, Sc, In and Cu and M″ is one selected from Nb and Ta), BixZnyNbzZrαO7 oxides satisfying relationships of 1.3<x<2.0, y<1.0, z<1.5, α<2.0, BixZnyNbzGdαO7 oxides satisfying 1.3<x<2.0, y<1.0, z<1.5,α<2.0 and BixNbyO4 oxides satisfying relationships of 1.3<x<2.0, y<1.0.
More preferably, the dielectric film has a thickness up to 2.0 μm.
Then according to the invention, a metal seed layer 27 is formed on the amorphous dielectric film 25 formed as described above via electroless plating.
In general, the elctroless plating involves a conditioner process which is a strong alkaline cleaning process, a pre-dip process, an activator process, a reducer process and final plating. However, the conditioner process which utilizes strong alkali of pH 12 and the pre-dip process which utilizes strong acid of pH 2-3 may potentially dissolve the dielectric film 25 formed.
Therefore, in repeated researches to overcome such a problem, the inventors have found that a desired metal seed layer 27 can be formed via electroless plating that involves only the activator process, reducer process and then final plating process exclusive of the conditioner process and pre-dip process as just described.
That is, first, as shown in
Preferably, the aforesaid process of the invention is carried out during longer duration than a conventional process. Specifically, the conventional process is maintained for 3 to 5 minutes to absorb Pd2+ onto a material, but in this invention, the process time desirably runs for 8 to 12 minutes. This prolonged process boosts Pd2+ absorption to increase its adhesion with the material, also improving reaction with Cu, i.e., the bath solution.
Subsequently, the stacked structure 20″ that has undergone the activator process is subjected to the reducer process. This process eliminates Sn, which is bonded to Pd of colloidal component and serves to protect Pd, thereby precipitating Pd metal onto a surface of the dielectric film 25. That is, this is a process of reducing oxidized Pd, i.e., Pd2+ back into Pd to be precipitated onto the dielectric film.
Here, the process of the invention lasts for 2 to 5 minutes.
Thereafter the stacked structure 20″ processed as just described is deposited in the bath solution for electroless plating and plated by a conventional method to form the metal seed layer 27 as shown in
Here, according to the invention, the metal seed layer 27 is preferably made of one selected from a group consisting of Cu, Ni and Cr, more preferably Cu.
Moreover, the metal seed layer 27 preferably has a thickness up to 0.3 μm.
Next, as shown in
Also, the upper electrode 29 is preferably made of one selected from a group consisting of Cu, Ni, Al, Pt, Ta and Ag. More preferably, the upper electrode 29 is made of Cu.
Preferably, the upper electrode 29 has a thickness up to 1.0 μm.
Then as shown in
As described above, the metal seed layer constituting the film capacitor is formed by electroless plating, thereby driving down manufacturing costs. Also, the printed circuit board with the film capacitor embedded therein can be manufactured effectively by a conventional build-up method for manufacturing a printed circuit board.
An example of the invention will be described in detail hereunder. It is intended, however, that the example is illustrative, but not limitative of the invention.
A lower electrode is formed to a thickness up to 2.0 μm on a substrate made of ABF SH9K by electroless plating and electrolytic plating. Then, a Bismuth Zinc Niobte (BZN) dielectric film having a composition expressed by Bi1.5Zn1Nb1.5O7 was deposited on the lower electrode by sputtering. Here, deposition was carried out for up to 3 hours at a temperature up to 200° C. and under a pressure up to 200 mTorr. The dielectric film was deposited to a thickness of about 300 nm.
Then, a metal seed layer was formed on the dielectric film by electroless plating exclusive of conventional. conditioner and pre-dip processes. Here, an activator process was carried out for 8 minutes at a temperature of 40° C. with pH of a bath solution ranging from 10.5 to 12.0. Moreover, a reducer process ran for 3 minutes.
Subsequently, an upper electrode was formed on the metal seed layer via conventional electrolytic plating. Then an insulating substrate of ABF SH9K was stacked on the upper electrode to produce an embedded film capacitor as shown in
As shown in
As set forth above, according to preferred embodiments of the invention, the invention employs electroless plating in place of a conventional PVD process to form a metal seed layer, thereby reducing manufacturing costs. In addition, the invention effectively produces a printed circuit board with a film capacitor embedded therein via a conventional build-up process.
While the present invention has been shown and described in connection with the preferred embodiments, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2005-0104674 | Nov 2005 | KR | national |
