Claims
- 1. A method for manufacturing a semiconductor device, comprising the steps of:
- (a) forming a first conductive pattern;
- (b) forming an insulation interlayer so that it covers the first conductive pattern;
- (c) forming, on the insulation interlayer, a conductive film on which a second conductive pattern is formed;
- (d) forming a contact hole, at a predetermined location, in both said conductive film and said insulation interlayer, so that said contact hole reaches said first conductive pattern;
- (e) forming a conductive layer for both covering the interior of the contact hole and directly covering the upper surface of the conductive film, so that a wiring is made between the conductive film and the first conductive pattern; and
- (f) subsequent to the formation of said conductive layer by step (e), selectively etching said conductive film and said conductive layer, to form the second conductive pattern.
- 2. The method according to claim 1, wherein said step for forming a conductive layer is performed by use of the CVD method.
- 3. The method according to claim 2, wherein poly-Si is used as said conductive layer.
- 4. The method according to claim 3, wherein Al issued as said conductive film for said second conductive pattern.
- 5. The method according to claim 3, wherein an MoSi.sub.2 film is used as said conductive film for said second conductive pattern.
- 6. The method according to claim 5, wherein said second conductive pattern is a DRAM bit line.
- 7. The method according to claim 1, wherein said conductive layer is formed so that said contact hole is completely filled with said conductive layer.
- 8. The method according to claim 1, wherein said first conductive pattern is a first wiring layer.
- 9. The method according to claim 1, wherein said first conductive pattern is an impurity diffusion layer formed in a semiconductor layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
61-103413 |
May 1986 |
JPX |
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Parent Case Info
This application is a Continuation of application Ser. No. 044,208 filed on Apr. 30, 1987, now abandoned.
US Referenced Citations (9)
Non-Patent Literature Citations (2)
Entry |
Smith et al., Proc. VLSI Multilevel Interconnect Conf., 403 (1986). |
Itoh et al., IEDM Tech. Digest, 1985, pp. 606-609. |
Continuations (1)
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Number |
Date |
Country |
Parent |
44208 |
Apr 1987 |
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