A method of manufacturing transistors of a first and second type on a substrate includes producing doped semiconductor areas with a first conductivity type in eventual contact areas of a first type of transistors, depositing a first intrinsic semiconductor layer over an entire surface, activating dopants in the semiconductor areas such that a contact area with the first conductivity type is produced in the intrincing semiconductor layer, depositing a gate dielectric, producing a gate electrode by depositing a first conductive layer and patterning the first conductive layer, performing ion doping with dopants to produce contact areas with a second conductivity type for a second type of transistor, depositing a passivation layer, opening contact openings, and depositing and patterning a second conductive layer.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1 through 10 are schematic depictions that demonstrate the manufacture of a transistor configuration according to the present invention with a sequence of corresponding steps of the manufacturing process.
Claims
1. A method of manufacturing transistors of a first and second type on a substrate, comprising the steps of producing doped semiconductor areas with a first conductivity type in eventual contact areas of a first type of transistors; depositing a first intrinsic semiconductor layer over an entire surface; activating dopants in the semiconductor areas such that a contact area with the first conductivity type is produced in the intrincing semiconductor layer; depositing a gate dielectric; producing a gate electrode by depositing a first conductive layer and patterning the first conductive layer; performing ion doping with dopants to produce contact areas with a second conductivity type for a second type of transistor; depositing a passivation layer; opening contact openings; and depositing and patterning a second conductive layer.
2. A method as defined in claim 1, wherein said producing the doped semiconductor areas includes depositing a doped semiconductor layer and then patterning it.
3. A method as defined in claim 1, wherein said producing the doped semiconductor layers includes depositing a second, intrinsing semiconductor layer, doping said second semiconductor layer, and patterning said doped second intrinsic semiconductor layer.
4. A method as defined in claim 3, wherein said doping the second intrincing semiconductor layer includes using ion doping.
5. A method as defined in claim 1; and further comprising activating the dopants of the doped semiconductor areas using a laser.
6. A method as defined in claim 1, wherein said depositing the first intrincing semiconductor layer includes depositing the first intrincing semiconductor layer as a layer selected from the group consisting of an amorphous layer and a microcrystalline layer, and subsequently crystallizing the deposited layer.
7. A method as defined in claim 6, wherein said subsequently crystallizing includes subsequently crystallizing the deposited layer so that said deposited layer forms a polycrystalline layer.
8. A method as defined in claim 1; and further comprising depositing a buffer layer on the substrate under doped semiconductor islands.
9. A method as defined in claim 1; and further comprising patterning the first intrincing semiconductor layer such that the semiconductor areas are retained, at least in contact areas for the first and second types of transistors.
10. A method as defined in claim 9, wherein said retaining includes retaining semiconductor islands that include contact areas and channels of the transistors are retained.
11. A method as defined in claim 1, wherein said ion doping includes ion doping with at least gate electrodes of the second type of transistor as a mask such that, in the contact areas with the first conductivity type, the first conductivity type is retained and the contact areas of the second type of transistors have a second conductivity type.
12. A method as defined in claim 1; and further comprising patterning the first conductivity layer such that the gate electrodes of the first type of transistor overlap at least part of the contact areas.
13. A method as defined in claim 1; and further comprising doping semiconductor islands so that the doped semiconductor islands are n+-doped, and areas having a low concentration of doping agent are produced by activating the dopants in a direction of a channel.
14. A method as defined in claim 1; and further comprising opening of contact holes to the first conductive layer and down to the contact areas by using only masking step.
15. A transistor configuration, comprising at least one first type of transistor and a second type of transistor; doped semiconductor areas with a first conductivity type in contact areas of the first type of transistors; a first conductivity layer doped with dopants of the doped semiconductor areas deposited thereon; a gate dielectric; a gate electrode composed of a first conductive layer; ion-doped contact areas of a second conductivity type of a second type of transistor; a passivation layer, and a second conductive layer.
16. A transistor configuration as defined in claim 15, wherein said first semiconductor layer is configured as an intrincing semiconductor layer that is doped in contact areas for the first type of transistors via subsequent activation, and out of which, after patterning, a channel region is formed for the first and second type of transistors.
17. A transistor configuration as defined in claim 15, wherein the contact areas of the second type of transistor are formed in the first semiconductor layer, with the ion doping of the contact areas being self-adjusted.
18. A transistor configuration as defined in claim 15, wherein the gate electrode of the first type of transistor overlaps the contact areas of this transistor.
19. A transistor configuration as defined in claim 15, wherein the transistor includes n+-doped contact areas with lower doping.
20. A transistor configuration as defined in claim 15, wherein contact holes of the first conductive layer and into the contact layers are opened in one masking step.
Patent Application
20070207576
