BACKGROUND
This disclosure relates generally to semiconductor devices, and more particularly to a method for manufacturing isolation structures in a semiconductor device.
As the density of components on a semiconductor device increases, the components are placed closer and closer to each other, and the need to properly isolate these components from each other arises. Isolation structures, such as shallow trench isolation (STI) structures and deep trench isolation (DTI) structures, are employed for this task. The manufacturing of these isolation structures poses a number of problems.
Isolation structures are typically manufactured using photolithography methods known in the art, followed by a time controlled etching process. Such time controlled etching processes are imprecise, resulting in poor control of the depth of the isolation trenches, which can narrow the tolerance ranges available to other parameters of device manufacture. In addition, the isolation trenches within a wafer will not be of a uniform depth, which can result in some trenches being too shallow and not isolating the components properly. These problems can lower the performance of the device. Furthermore, isolation trenches from wafer to wafer and from wafer lot to wafer lot cannot be made of a uniform depth, reducing the repeatability of device performance across wafers and wafer lots.
Accordingly, it would be desirable to provide an improved method for manufacturing isolation structures in a semiconductor device absent the disadvantages found in the prior methods discussed above.
BRIEF DESCRIPTION OF THE DRAWINGS
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 is a cross sectional view illustrating an embodiment of the method with ions being implanted below the surface of a substrate.
FIG. 2 is a cross sectional view illustrating an embodiment of the method with a layer formed below the surface of a substrate.
FIG. 3 is a cross sectional view illustrating an embodiment of the method with a layer of photoresist formed on the surface of a substrate.
FIG. 4 is a cross sectional view illustrating an embodiment of the method with light shined through a patterned mask and onto a layer of photoresist on the surface of a substrate.
FIG. 5 is a cross sectional view illustrating an embodiment of the method with sections of photoresist removed from the surface of a substrate.
FIG. 6 is a cross sectional view illustrating an embodiment of the method with isolation structures formed in a substrate.
FIG. 7 is a cross sectional view illustrating an embodiment of the method with a layer of photoresist formed on the surface of a substrate.
FIG. 8 is a cross sectional view illustrating an embodiment of the method with light shined through a patterned mask and onto a layer of photoresist on the surface of a substrate.
FIG. 9 is a cross sectional view illustrating an embodiment of the method with sections of photoresist removed from the surface of a substrate.
FIG. 10 is a cross sectional view illustrating an embodiment of the method with ions being implanted below the surface of a substrate through areas of the surface not covered with photoresist.
FIG. 11 is a cross sectional view illustrating an embodiment of the method with a sectional layer formed below the surface of a substrate.
FIG. 12 is a cross sectional view illustrating an embodiment of the method with light shined through a patterned mask and onto a layer of photoresist on the surface of a substrate.
FIG. 13 is a cross sectional view illustrating an embodiment of the method with sections of photoresist removed from the surface of a substrate.
FIG. 14 is a cross sectional view illustrating an embodiment of the method with isolation structures formed in a substrate.
DETAILED DESCRIPTIONS
Referring to FIG. 1, a semiconductor device 100 includes a substrate 102 with a surface 104. A plurality of ions 106 are implanted approximately a distance A below the surface 104 of substrate 102. The plurality of ions 106 may be implanted using methods known in the art, such as Separation by Implantation of Oxygen (SIMOX) technology, and can be ions of a variety of elements including, but not limited to, oxygen ions, nitrogen ions, and combinations thereof. For example, an implantation of oxygen ions into a P-type substrate may exhibit a concentration of less than 1.4×1017 O+ ions/cm2
Referring now to FIG. 2, following the ion implantation, device 100 is annealed. Annealing device 100 results in the growth of a layer 106 approximately a distance A below the surface 104 of substrate 102. Depending on the type of ions implanted and the substrate used, layer 106 may be composed of a number of materials including, but not limited to, SiO2, SiN, and SiOxNy. For example, an annealing of oxygen ions implanted in a P-type substrate may occur below 1300 degrees C. to grow layer 106 to a thickness of 200-400 A.
Referring now to FIG. 3, a layer of photoresist 108 is deposited on surface 104 of substrate 102. Photoresist 108 may be deposited using methods known in the art.
Referring now to FIG. 4, a patterned mask 110 is placed over the layer of photoresist 108, and a light 112 is shined on the patterned mask 110. Light 112 passes through sections of patterned mask 110 and onto photoresist 108. Physical properties of photoresist 108 are changed by exposure to light 112.
Referring now to FIG. 5, the photoresist 108 is developed, which removes section of photoresist 108 from surface 104 which have been exposed to light 112, exposing a surface section 114 and 116 on substrate 102. Alternative types of photoresist 108 may be used such that development would remove sections of photoresist 108 from the surface 104 of substrate 102 which had not been exposed to light 112.
Referring now to FIG. 6, following the removal of photoresist 108 from surface 104 of substrate 102, an isolation structure 118 and an isolation structure 120 may be etched into substrate 102 through the exposed portions of surface 104, such as sections 114 and 116 as illustrated in FIG. 5, on substrate 102 using methods known in the art. However, the etchant will be stopped by layer 106, which will provide isolation structures 118 and 120 of approximately the same depth A. In an exemplary embodiment, the isolation structures 118 and 120 may be shallow trench isolation structures, which include isolation structures exhibiting a depth with a range of approximately 0.1 to approximately 5 μm. In an exemplary embodiment, the isolation structures 118 and 120 may be shallow trench isolation structures, which include isolation structures exhibiting a depth with a range of approximately 0.1 to approximately 5 μm.
Referring now to FIG. 7, in an alternative embodiment, a semiconductor device 200 includes a substrate 202 with a surface 204. A layer of photoresist 206 is deposited on surface 204 of substrate 202. Photoresist 206 may be deposited using methods known in the art.
Referring now to FIG. 8, a patterned mask 208 is placed over the layer of photoresist 206, and a light 210 is shined on the patterned mask 208. Light 210 passes through sections of patterned mask 208 and onto photoresist 206. Physical properties of photoresist 204 are changed by exposure to light 210.
Referring now to FIG. 9, the photoresist 206 is developed which removes section of photoresist 206 from surface 204 which have been exposed to light 210, exposing a surface section 212 and 214 on substrate 202. Alternative types of photoresist 206 may be used such that development would remove sections of photoresist 206 from the surface 204 of substrate 202 which had not been exposed to light 210.
Referring now to FIG. 10, a plurality of ions 216 are implanted approximately a distance A below the surface 204 of substrate 202. The plurality of ions 216 are implanted through the exposed surface 204, such as sections 212 and 214 as illustrated in FIG. 9, of substrate 202, resulting in implanted ion sections 218 and 220. The plurality of ions 216 may be implanted using methods known in the art, such as Separation by Implantation of Oxygen (SIMOX) technology, and can be ions of a variety of elements including, but not limited to, oxygen ions, nitrogen ions, and combinations thereof. For example, an implantation of oxygen ions into a P-type substrate may exhibit a concentration of less than 1.4×1017 O+ ions/cm2.
Referring now to FIG. 11, the photoresist 206 is removed from surface 204 of substrate 202 and device 200 is annealed. Annealing the device 200 results in the growth of a layer section 222 and 224 approximately a distance A below the surface 204 of substrate 202. Depending on the type of ions implanted and the substrate used, layer section 222 and 224 may be composed of a number of materials including, but not limited to, SiO2, SiN, and SiOxNy. For example, an annealing of oxygen ions implanted in a P-type substrate may occur below 1300 C to grow layer sections 222 and 224 to a thickness of 200-400 A.
Referring now to FIG. 12, after growth of layer sections 222 and 224, a layer of photoresist 226 is deposited on the surface 204 of substrate 202. A patterned mask 228 is placed over the layer of photoresist 226 and a light 230 is shined on the patterned mask 228. Light 230 passes through sections of patterned mask 228 and onto photoresist 226. Physical properties of photoresist 226 are changed by exposure to light 230.
Referring now to FIG. 13, photoresist 226 is developed, which removes sections of photoresist 226 from surface 204 which have been exposed to light 230, exposing a surface section 232 and 234 on substrate 202. Alternative types of photoresist 226 may be used such that development would remove sections of photoresist 226 from the surface 204 of substrate 202 which had not been exposed to light 230.
Referring now to FIG. 14, following the removal of photoresist 226 from surface 204 of substrate 202, an isolation structure 236 and an isolation structure 238 may be etched into substrate 202 through the exposed portions of surface 204, such as sections 232 and 234 as illustrated in FIG. 13, on substrate 202 using methods known in the art. However, the etchant will be stopped by layer sections 222 and 224, which will provide isolation structures 236 and 238 of approximately the same depth A. In an exemplary embodiment, the isolation structures 236 and 238 may be shallow trench isolation structures, which include isolation structures exhibiting a depth with a range of approximately 0.1 to approximately 5 μm. In an exemplary embodiment, the isolation structures 236 and 238 may be shallow trench isolation structures, which include isolation structures exhibiting a depth with a range of approximately 0.1 to approximately 5 μm.
It is understood that variations may be made in the foregoing without departing from the scope of the invention. Furthermore, the elements and teachings of the various illustrative embodiments may be combined in whole or in part some or all of the illustrative embodiments.
Although only a few exemplary embodiments of this invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the following claims.
Patent Application
20050277262
