Patent Grant
6858498
The invention relates to a method for manufacturing memories, and in particular, to a method for manufacturing memories, in which the sources, drains, and gates of the memories are defined by self-alignment processes.
In general, a conventional non-volatile memory cell includes a source, a drain, a control gate, and a floating gate. The memory cell typically performs in three operating modes, including a reading mode, a programming mode and an erasing mode, with electrons injected into or released from the floating gate. The floating gate traps the electrons, so that the data stored in the memory cell can be recorded as the entire memory is powered off. The floating gate and control gate consist of the gate of the memory cell, which are generally a split gate type, a stacked gate type, or a combination thereof.
A conventional memory device usually includes a memory array, which has a plurality of memory cells. A major obstacle to manufacturing the memory array has been the alignment of various components such as sources, drains, control gates, and floating gates. As the integration of semiconductor processes increases, which reduces the largest lithographic features, the need for precise alignment becomes more critical. Alignment of the various parts also determines the potential product yield.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step. Accordingly, the structure of the memory device can be accurately aligned to improve the production yield of the memory device. U.S. Pat. No. 5,242,848 discloses a self-aligned method of making a memory device, which is described herein below with reference to
Finally, as shown in
In the manufacturing of the split gate non-volatile memory cell (as shown in FIG. 1J), the most critical point is the dimensions of the select transistor, which is defined between the floating gate 23 and the drain region 16. U.S. Pat. No. 5,242,848 discloses a method for defining the select transistor, and there are, however, some errors occurred when performing this method, such as:
In brief, to manufacture the floating gate, control gate, source and drain of the conventional non-volatile memory cell, the above-mentioned error values, such as the ΔCD1, ΔCD2 and ΔCD3, must be considered. Thus, a total error value ΔCDt can be obtained according to the following equation:
ΔCDt={(ΔCD1)2+(ΔCD2)2+(ΔCD3) 2}0.5
It should be noted that as the scale of integration of semiconductor processing increases, reducing the lithographic features, dimension control of various parts and the alignment errors there between profoundly affect yield of the manufacturing of the semiconductor memory cell. Thus, the need for precisely controlling the total error value ΔCDt becomes increasingly critical.
U.S. Pat. No. 6,329,685 discloses a self-aligned method of forming a memory array, which can control the mentioned total error value ΔCDt so as to improve the controllability of the dimension of the select transistor.
In summary, the above-mentioned processes can pre-define the positions for the control gate 41 and the second doped region 35. Furthermore, the control gates 41 are formed with an etching process, and the opposite control gates 41 are used as masks to define the area and position of each second doped region 35. This process, however, has the following disadvantages:
First, the complicated stacked structure as shown in
For this reason, it is a subjective of semiconductor memory industries to provide a method for manufacturing a memory, which can reduce the total error value while manufacturing a memory so as to increase the controllability of the dimension of the select transistor.
It is therefore an objective of the invention to provide a method for manufacturing a memory, which can reduce the total error value while manufacturing a memory.
To achieve the above-mentioned objective, a method for manufacturing a memory includes the following steps of:
As mentioned above, the method for manufacturing a memory of the invention defines the floating gate region and the relative positions of the floating gate region and drain region, which can define the dimension of the select transistor, with a single photolithography process. Then, the method for manufacturing a memory of the invention utilizes self-aligned implantation to implant ions into the defined source region and drain region. Thus, the formation of the control gate does not affect the positions (and the relative positions) of the source region and drain region. Accordingly, the dimension of the select transistor would not have errors according to the error values ΔCD2 and ΔCD3. The inventor calls the method of the invention “pattern transferring method”.
The invention will become more fully understood from the detailed description given herein below illustration only, and thus is not limitative of the present invention, and wherein:
The method for manufacturing a memory according to the preferred embodiments of the invention will be described herein below with reference to the accompanying drawings, wherein the same reference numbers refer to the same elements.
Referring to
As shown in
Referring to
Thereafter, a plurality of spacers 22a can be formed on the sidewalls of the residual silicon nitride layer 70 (see FIG. 3C). To form the spacers, another polysilicon layer is deposited over the substrate, and is then etched back. Therefore, the spacers 22a can be defined aside the silicon nitride layer 70, which is used as a mask. In this case, a sharp curved-up charge injection region, which can increase the electron tunneling capability, can be formed using conventional deposition and etching processes.
The polysilicon layer 22 located in the second patterned region 82 is then etched away. In this embodiment, a photoresist layer 50 is formed over the substrate 10, and is then patterned to expose a portion of the polysilicon layer 22 located in the second patterned region 82 and parts of the silicon nitride layer 70 adjacent to the second patterned region 82 (see FIG. 3D). Thereafter, a self-aligned etching process is performed using the photoresist layer 50 and parts the silicon nitride layer 70 as masks. As shown in
With reference to
Please refer to FIG. 3G. The substrate 10 is oxidized to form a first silicon oxide region 72a in the first patterned region 81 and a second silicon oxide region 72b in the second patterned region 82. In the current embodiment, the photoresist layer 50 is first stripped away. A thermal oxidation is then performed and the silicon nitride layer 70 is used as a mask. The polysilicon layer 22 in the opening of the silicon oxide layer 70 and the exposed silicon oxide layer 20 are thermally oxidized to grow the first silicon oxide region 72a and second silicon oxide region 72b. The first silicon oxide region 72a is formed on the first polysilicon layer 22. The second silicon oxide region 72b is formed above the first-doped region 16′. In detail, the dimension and location underneath the first silicon oxide region 72a are those of the gate region of the memory, while the dimension and location underneath the second silicon oxide region 72b are those of the drain region of the memory.
The residual silicon nitride layer 70 is then stripped away as shown in
Using the first silicon oxide region 72a as a mask, the polysilicon layer 22 is etched to form a first gate 23′, which is located in the first patterned region 81 underneath the first silicon oxide region 72a (see FIG. 3I). In this step, the first silicon oxide region 72a is used as a mask, and a self-aligned anisotropic etching process; e.g., a reactive ion etch, is applied to selectively etch the exposed polysilicon layer 22, which is not directly beneath the first silicon oxide region 72a. This leaves a region of polysilicon layer defined by the first silicon oxide region 72a and forms the first gate 23′. The distance between the first gate 23′ and the first doped region 16′ is equal to the predetermined length mentioned above. The first gate 23′ of the embodiment is used as the previously mentioned floating gate 23.
Finally, ion implantation is performed, so that a second doped region 14′ is formed adjacent to the first gate 23′. Accordingly, the first gate 23′ is located between the first doped region 16′ and the second doped region 14′. In the present embodiment, another photoresist layer 52 is spun over the substrate 10 and is patterned. The patterned photoresist layer 52 and the first silicon oxide region 72a are used as masks to perform an ion implanting process. The second doped region 14′ is defined accordingly. The second doped region 14′ of the embodiment is equal to the previously mentioned source region 14.
As mentioned above, the method for manufacturing a memory of the invention can accurately define the dimensions and locations of the first gate 23′, first doped region 16′ and second doped region 14′. Therefore, the dimension of the select transistor can be defined. In addition, the channel length between the first doped region 16′ and second dope region 14′ can be accurately controlled.
After the second doped region 14′ is formed, the method of the invention further includes the following steps. The photoresist layer 52 is removed, and the entire structure is oxidized to form a second insulating layer. A second polysilicon layer is then deposited on the structure, and is selectively etched to form a second gate 25 over the first gate 23′ (see FIG. 3K). Moreover, the second gate 25 can be further etched to expose the first doped region 16′ so as to form a contact hole of the first doped region 16′ (see FIG. 3L). It should be noted that the second gate 25 could be formed similar to the above-mentioned control gate 29 (see 3M). Thus, the second gate 25 includes a first portion 25a deposed over the first gate 23′, and a second portion 25b, which is disposed over the silicon oxide layer 20 and is closely adjacent to the first gate 23′. The second portion 25b serves as a select transistor adjacent to the first gate 23′.
In addition, the method for manufacturing a memory of the invention may be applicable when manufacturing a memory of different structures. Thus, an additional embodiment of the invention will be described herein below.
Referring to
As shown in
Referring to
Thereafter, the polysilicon layer 22 located in the second patterned region 82 is etched away. In this embodiment, a photoresist layer 50 is formed over the substrate 10, and is then patterned to expose a portion of the polysilicon layer 22 located in the second patterned region 82 and parts of the silicon nitride layer 70 adjacent to the second patterned region 82 (see FIG. 4C). A self-aligned etching process is then performed using the photoresist layer 50 and parts of the silicon nitride layer 70 as masks. As shown in
With reference to
The residual silicon nitride layer 70 is then stripped away as shown in
Using the first silicon oxide region 72a as a mask, the polysilicon layer 22, dielectric layer 27 and polysilicon layer 28 are etched to form a stacked gate. The stacked gate is underneath the first silicon oxide region 72a located in the first patterned region 81 and includes a first gate 23′ and a third gate 28′ (see FIG. 31). In this step, the first silicon oxide region 72a is used as a mask, and a self-aligned anisotropic etching process; e.g., a reactive ion etch, is applied to selectively etch the exposed polysilicon layer 22, dielectric layer 27 and polysilicon layer 28, which are not directly located beneath the first silicon oxide region 72a. This leaves the stacked gate defined under the first silicon oxide region 72a. The stacked gate includes the first gate 23′, third gate 28′ and the dielectric layer 27 sandwiched between the first gate 23′ and third gate 28′. The distance between the stacked gate and the first doped region 16′ is equal to the predetermined length mentioned above. The third gate 28′ is a floating gate, and the first gate 23′ is a control gate positioned above the floating gate.
Finally, ion implantation is performed, so that a second doped region 14′ is formed adjacent to the stacked gate. The stacked gate is located between the first doped region 16′ and the second doped region 14′. In the present embodiment, another photoresist layer 52 is spun over the substrate 10 and is patterned. The patterned photoresist layer 52 and the first silicon oxide region 72a are used as masks to perform an ion implanting process. Accordingly, the second doped region 14′ is defined. The second doped region 14′ of the embodiment functions as the previously mentioned source region 14.
After the second doped region 14′ is formed, this method may include the additional steps as described herein below. The photoresist layer 52 is removed, and the entire structure is oxidized to form an oxide layer. A second polysilicon layer is then deposited over the substrate, and is selectively etched to form a second gate 25 over the stacked gate (see FIG. 4J). The second gate 25 consists of a select transistor adjacent to the stacked gate. The second polysilicon layer, having a thickness of 1500 to 4000 angstroms, can be made of polysilicon or polycide. Moreover, the second gate 25 can be further etched to expose the first doped region 16′ so as to form a contact hole of the first doped region 16′ (not shown). It should be noted that this step is similar to the above-mentioned step referring to
In summary, the method for manufacturing a memory of the invention defines the floating gate region and the relative positions of the floating gate region and drain region, which can define the dimension of the select transistor, with a single photolithography process. Then, this method utilizes a self-aligned ion implanting process to implanting ions into the defined source region and drain region. Thus, the positions (and the relative positions) of the source region and drain region can be controlled accurately. Accordingly, the dimension control of the select transistor would not include the errors of ΔCD2 (dimension error of the control gate) and ΔCD3 (misalignment between the control gate and floating gate) existed in the conventional method. The total error value while manufacturing a memory can then be reduced sufficiently, and the controllability of the select transistor can be increased, resulting in the increase of the production yield.
Although the invention has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments, will be apparent to persons skilled in the art. It is, therefore, contemplated that the appended claims will cover all modifications that fall within the true scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 92117859 A | Jun 2003 | TW | national |
This nonprovisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 092117859 filed in Taiwan on Jun. 30, 2003, which is herein incorporated by reference.
| Number | Name | Date | Kind |
|---|---|---|---|
| 5242848 | Yeh | Sep 1993 | A |
| 6174772 | Hsieh et al. | Jan 2001 | B1 |
| 6194269 | Sung et al. | Feb 2001 | B1 |
| 6200859 | Huang et al. | Mar 2001 | B1 |
| 6329685 | Lee | Dec 2001 | B1 |
| 6627946 | Wang | Sep 2003 | B2 |
| Number | Date | Country | |
|---|---|---|---|
| 20040266104 A1 | Dec 2004 | US |
