METHOD FOR MANUFACTURING PRINTED WIRING BOARD

Abstract

A method for manufacturing a printed wiring board includes forming an opening through a core substrate such that the opening is formed to accommodate first electronic components and second electronic components, pasting a tape on a surface of the substrate such that the tape closes the opening of the substrate on one side, mounting the first electronic components on the tape exposed in the opening of the substrate such that the first electronic components are positioned inside the opening of the substrate, mounting the second electronic components on the tape exposed in the opening of the substrate such that the second electronic components are positioned inside the opening of the substrate, filling resin in spaces formed between the first and second electronic components, spaces between the first electronic components and the substrate, and spaces between the second electronic components and the substrate, and removing the tape from the substrate.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2018-103724, filed May 30, 2018, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a method for manufacturing a printed wiring board for accommodating first electronic components and second electronic components in an opening.

Description of Background Art

Japanese Patent Laid-Open Publication No. 2012-039050 describes a metal substrate in which Peltier elements are embedded. The entire contents of this publication are incorporated herein by reference.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a method for manufacturing a printed wiring board includes forming an opening through a core substrate such that the opening is formed to accommodate first electronic components and second electronic components, pasting a tape on a surface of the core substrate such that the tape closes the opening of the core substrate on one side, mounting the first electronic components on the tape exposed in the opening of the core substrate such that the first electronic components are positioned inside the opening of the core substrate, mounting the second electronic components on the tape exposed in the opening of the core substrate such that the second electronic components are positioned inside the opening of the core substrate, filling resin in spaces formed between the first electronic components and the second electronic components, spaces between the first electronic components and the core substrate, and spaces between the second electronic components and the core substrate, and removing the tape from the core substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

FIG. 1A is a cross-sectional view of a printed wiring board according to a first embodiment of the present invention;

FIGS. 1B and 1C are cross-sectional views of electronic components;

FIGS. 1D and 1E are cross-sectional views of via conductors;

FIGS. 2A and 2B illustrate a method for accommodating electronic components of the first embodiment;

FIG. 2C illustrates an arrangement of the electronic components;

FIGS. 3A-3D are manufacturing process diagrams of the printed wiring board of the first embodiment;

FIGS. 4A-4C are manufacturing process diagrams of the printed wiring board of the first embodiment;

FIGS. 5A and 5B are manufacturing process diagrams of the printed wiring board of the first embodiment;

FIG. 6A is a cross-sectional view of a printed wiring board according to a second embodiment of the present invention;

FIG. 6B is a schematic diagram illustrating a part of for-built-in-component wirings;

FIGS. 6C and 6D illustrate positions of the electronic components;

FIGS. 7A-7C illustrate a method for accommodating electronic components of the second embodiment; and

FIGS. 8A and 8B are plan views illustrating wirings connected to the electronic components.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.

First Embodiment

FIG. 1A is a cross-sectional view of a printed wiring board 10 of a first embodiment. The printed wiring board 10 has a core substrate 30 having a fifth surface (F) and a sixth surface (S) on an opposite side with respect to the fifth surface (F), a first build-up layer (55F) formed on the fifth surface (F) of the core substrate, and a second build-up layer (55S) formed on the sixth surface (S) of the core substrate.

The core substrate 30 has a core material (insulating substrate) (20z) having the fifth surface (F) and the sixth surface (S) on an opposite side with respect to the fifth surface (F), a fifth conductor layer (34F) formed on the fifth surface of the core material (20z), a sixth conductor layer (34S) formed on the sixth surface (S) of the core material (20z), and through-hole conductors 36 connecting the fifth conductor layer (34F) and the sixth conductor layer (34S) to each other. The core substrate 30 has an opening 31 that extends from the fifth surface (F) to the sixth surface (S). Multiple first electronic components (32P) and multiple second electronic components (32N) are accommodated in the opening 31. Spaces between the first electronic components (32P) and the second electronic components (32N) are filled with a resin 53. Spaces between the first electronic components (32P) and the core substrate 30 are filled with the resin 53. Spaces between the second electronic components (32N) and the core substrate 30 are filled with the resin 53. The first electronic components (32P) and the second electronic components (32N) are fixed to the core substrate 30 by the resin 53.

FIG. 1B illustrates one of the first electronic components (32P).

Each of the first electronic components (32P) has electrodes (32P1, 32P2) at two ends thereof. The first electronic components (32P) are each formed of a P-type semiconductor element 321 having a first surface (F1) and a second surface (S1) on an opposite side with respect to the first surface (F1), the first electrode (32P1) on the first surface (F1), and the second electrode (32P2) on the second surface (S1). The P-type semiconductor element 321 is sandwiched between the first electrode (32P1) and the second electrode (32P2).

The first electrode (32P1) faces the fifth surface (F) of the core substrate 30, and the second electrode (32P2) faces the sixth surface (S) of the core substrate 30. The first electronic components are each an N-type thermoelectric element or a P-type thermoelectric element. The P-type semiconductor element is preferably a P-type thermoelectric element.

The first electronic components (32P) are embedded in the opening 31 such that the first electrodes (32P1) face the fifth surface (F).

FIG. 1C illustrates one of the second electronic components (32N).

Each of the second electronic components (32N) has electrodes (32P3, 32P4) at two ends thereof. For example, the second electronic components (32N) are each formed of an N-type semiconductor element 322 having a third surface (F2) and a fourth surface (S2) on an opposite side with respect to the third surface (F2), the third electrode (32P3) on the third surface (F2), and the fourth electrode (32P4) on the fourth surface (S2). The N-type semiconductor element 322 is sandwiched between the third electrode (32P3) and the fourth electrode (32P4).

The third electrode (32P3) faces the fifth surface (F) of the core substrate 30, and the fourth electrode (32P4) faces the sixth surface (S) of the core substrate 30. The N-type semiconductor element is preferably an N-type thermoelectric element. The second electronic components (32N) are embedded in the opening 31 such that the third electrodes (32P3) face the fifth surface (F).

The first build-up layer (55F) has a first resin insulating layer (50F) formed on the fifth surface (F) of the core substrate 30 and on the fifth conductor layer (34F), a first conductor layer (58F) formed on the first resin insulating layer (50F), a third resin insulating layer (150F) formed on the first conductor layer (58F) and on the first resin insulating layer (50F), and a third conductor layer (158F) formed on the third resin insulating layer (150F). The first resin insulating layer (50F) covers the opening 31. The resin 53 and the first resin insulating layer (50F) are integrally formed. Spaces between the first electronic components (32P) and a side wall of the core substrate 30 exposed from the opening 31 are filled with a resin originating from the first resin insulating layer (50F). Spaces between the second electronic components (32N) and the side wall of the core substrate 30 exposed from the opening 31 are filled with the resin originating from the first resin insulating layer (50F). Spaces between the first electronic components (32P) and the second electronic components (32N) are filled with the resin originating from the first resin insulating layer (50F). A component originating from the first resin insulating layer (50F) forms the resin 53. The resin 53 can contain a resin and inorganic particles originating from the first resin insulating layer (50F).

The first conductor layer (58F) has a first conductor circuit (58FW) formed directly on the opening 31, and an on-core-material first conductor circuit (58FC) formed directly on the core material (20z). Adjacent first electronic components (32P) and second electronic components (32N) are connected to each other by the first conductor circuit (58FW).

FIG. 8A is a plan view illustrating the first conductor circuit (58FW). The first conductor circuit (58FW) includes on-first-electrode first conductor circuits (58FW1) respectively covering the first electrodes (32P1), on-third-electrode first conductor circuits (58FW3) respectively covering the third electrodes (32P3), and first wirings (58fW) each connecting one of the on-first-electrode first conductor circuits (58FW1) to one of the on-third-electrode first conductor circuits (58FW3). The on-first-electrode first conductor circuits (58FW1) are respectively positioned on the first electrodes (32P1), and a size of each of the on-first-electrode first conductor circuits (58FW1) is larger than a size of each of the first electrodes (32P1). The on-third-electrode first conductor circuits (58FW3) are respectively positioned on the third electrodes (32P3), and a size of each of the on-third-electrode first conductor circuits (58FW3) is larger than a size of each of the third electrodes (32P3). A width (58fWD) of each of the first wirings (58fW) is equal to a width (58FWD1) of each of the on-first-electrode first conductor circuits (58FW1). Or, the width (58fWD) of each of the first wirings (581W) is smaller than the width (58FWD1) of each of the on-first-electrode first conductor circuits (58FW1). The width (58fWD) of each of the first wirings (581W) is equal to a width (58FWD3) of each of the on-third-electrode first conductor circuits (58FW3). Or, the width (58fWD) of each of the first wirings (58fW) is smaller than the width (58FWD3) of each of the on-third-electrode first conductor circuits (58FW3).

Dotted lines in the on-first-electrode first conductor circuits (58FW1) respectively indicate outer peripheries of top parts of for-first-electrode first via conductors (60F1). The on-first-electrode first conductor circuits (58FW1) are connected to the first electrodes (32P1) by the multiple for-first-electrode first via conductors (60F1).

Dotted lines in the on-third-electrode first conductor circuits (58FW3) respectively indicate outer peripheries of top parts of for-third-electrode first via conductors (60F3). The on-third-electrode first conductor circuits (58FW3) are connected to the third electrodes (32P3) by the multiple for-third-electrode first via conductors (60F3).

One on-first-electrode first conductor circuit (58FW1) is formed on one first electrode (32P1). One on-third-electrode first conductor circuit (58FW3) is formed on one third electrode (32P3).

The first build-up layer (55F) further has first via conductors (60F) penetrating the first resin insulating layer (50F) and third via conductors (160F) penetrating the third resin insulating layer (150F). The first via conductors (60F) include via conductors (for-fifth-conductor-layer first via conductors) (60F5) that connect the fifth conductor layer (34F) to the on-core-material first conductor circuit (58FC), the via conductors (the for-first-electrode first via conductors) (60F1) that connect the first electrodes (32P1) to the on-first-electrode first conductor circuits (58FW1), and the via conductors (the for-third-electrode first via conductors) (60F3) that connect the third electrodes (32P3) to the on-third-electrode first conductor circuits (58FW3). The number of the for-first-electrode first via conductors (60F1) that connect one of the first electrodes (32P1) to one of the on-first-electrode first conductor circuits (58FW1) is 2 or more. For example, the number of the for-first-electrode first via conductors (60F1) reaching one of the first electrodes (32P1) is 20 or more. A heat dissipation effect can be increased. Connection reliability can be increased even when the electronic components 32 expand or contract. The number of the for-third-electrode first via conductors (60F3) that connect one of the third electrodes (32P3) to one of the on-third-electrode first conductor circuits (58FW3) is 2 or more. For example, the number of the for-third-electrode first via conductors (60F3) reaching one of the third electrodes (32P3) is 20 or more. The heat dissipation effect can be increased. The connection reliability can be increased even when the electronic components 32 expand or contract.

The first resin insulating layer (50F) has a bottom surface (BF) opposing the fifth surface (F) and a top surface (TF) on an opposite side with respect to the bottom surface (BF). Then, the for-fifth-conductor-layer first via conductors (60F5), the for-first-electrode first via conductors (60F1) and the for-third-electrode first via conductors (60F3) each have a top diameter (TDF) at a position of the top surface (TF). The top diameter (TDF) of each of the for-fifth-conductor-layer first via conductors (60F5), the top diameter (TDF) of each of the for-first-electrode first via conductors (60F1), and the top diameter (TDF) of each of the for-third-electrode first via conductors (60F3) are substantially equal to each other. The top diameter (TDF) is illustrated in FIG. 1D.

The second build-up layer (55S) has a second resin insulating layer (50S) formed on the sixth surface (S) of the core substrate 30 and on the sixth conductor layer (34S), a second conductor layer (58S) formed on the second resin insulating layer (50S), a fourth resin insulating layer (150S) formed on the second conductor layer (58S) and on the second resin insulating layer (50S), and a fourth conductor layer (158S) formed on the fourth resin insulating layer (150S).

The second conductor layer (58S) has a second conductor circuit (58SW) formed directly on the opening 31, and an on-core-material second conductor circuit (58SC) formed directly on the core material (20z).

Adjacent first electronic components (32P) and second electronic components (32N) are connected to each other by the second conductor circuit (58SW).

FIG. 8B is a plan view illustrating the second conductor circuit (58SW). The second conductor circuit (58SW) includes on-second-electrode second conductor circuits (58SW2) respectively covering the second electrodes (32P2), on-fourth-electrode second conductor circuits (58SW4) respectively covering the fourth electrodes (32P4), and second wirings (58sW) each connecting one of the on-second-electrode second conductor circuits (58SW2) to one of the on-fourth-electrode second conductor circuits (58SW4). The on-second-electrode second conductor circuits (58SW2) are respectively positioned on the second electrode (32P2), and a size of each of the on-second-electrode second conductor circuits (58SW2) is larger than a size of each of the second electrodes (32P2). The on-fourth-electrode second conductor circuits (58SW4) are respectively positioned on the fourth electrode (32P4), and a size of each of the on-fourth-electrode second conductor circuits (58SW4) is larger than a size of each of the fourth electrodes (32P4). A width (58sWD) of each of the second wirings (58sW) is equal to a width (58SWD2) of each of the on-second-electrode second conductor circuits (58SW2). Or, the width (58sWD) of each of the second wirings (58sW) is smaller than the width (58SWD2) of each of the on-second-electrode second conductor circuits (58SW2). The width (58sWD) of each of the second wirings (58sW) is equal to a width (58SWD4) of each of the on-fourth-electrode second conductor circuits (58SW4). Or, the width (58sWD) of each of the second wirings (58sW) is smaller than the width (58SWD4) of each of the on-fourth-electrode second conductor circuits (58SW4).

Dotted lines in the on-second-electrode second conductor circuits (58SW2) respectively indicate outer peripheries of top parts of for-second-electrode second via conductors (60S2). The on-second-electrode second conductor circuits (58SW2) are connected to the second electrodes (32P2) by the multiple for-second-electrode second via conductors (60S2).

Dotted lines in the on-fourth-electrode second conductor circuit (58SW4) respectively indicate outer peripheries of top parts of for-fourth-electrode second via conductors (60S4). The on-fourth-electrode second conductor circuits (58SW4) are connected to the fourth electrodes (32P4) by the multiple for-fourth-electrode second via conductors (60S4).

One on-second-electrode second conductor circuit (58SW2) is fanned on one second electrode (32P2). One on-fourth-electrode second conductor circuit (58SW4) is formed on one fourth electrode (32P4).

The second build-up layer (55S) further has second via conductors (60S) penetrating the second resin insulating layer (50S) and fourth via conductors (160S) penetrating the fourth resin insulating layer (150S). The second via conductors (60S) include via conductors (for-sixth-conductor-layer second via conductors) (60S6) that connect the sixth conductor layer (34S) to the on-core-material second conductor circuit (58SC), the via conductors (the for-second-electrode second via conductors) (60S2) that connect the second electrodes (32P2) to the on-second-electrode second conductor circuits (58SW2), and the via conductors (the for-fourth-electrode second via conductors) (60S4) that connect the fourth electrodes (32P4) to the on-fourth-electrode second conductor circuits (58SW4). The number of the for-second-electrode second via conductors (60S2) that connect one second electrode (32P2) to one on-second-electrode second conductor circuit (58SW2) is 2 or more. For example, the number of the for-second-electrode second via conductors (60S2) reaching one of the second electrodes (32P2) is 20 or more. The heat dissipation effect can be increased. The connection reliability can be increased even when the electronic components 32 expand or contract. The number of the for-fourth-electrode second via conductors (60S4) that connect one fourth electrode (32P4) to one on-fourth-electrode second conductor circuit (58SW4) is 2 or more. For example, the number of the for-fourth-electrode second via conductors (60S4) reaching one of the fourth electrodes (32P4) is 20 or more. The heat dissipation effect can be increased. The connection reliability can be increased even when the electronic components 32 expand or contract.

The second resin insulating layer (505) has a bottom surface (BS) opposing the sixth surface (S) and a top surface (TS) on an opposite side with respect to the bottom surface (BS). Then, the for-sixth-conductor-layer second via conductors (60S6), the for-second-electrode second via conductors (60S2) and the for-fourth-electrode second via conductors (60S4) each have a top diameter (TDS) at a position of the top surface (TS). The top diameter (TDS) of each of the for-sixth-conductor-layer second via conductors (60S6), the top diameter (TDS) of each of the for-second-electrode second via conductors (60S2) and the top diameter (TDS) of each of the for-fourth-electrode second via conductors (60S4) are substantially equal to each other. The top diameter (TDS) is illustrated in FIG. 1E.

A second solder resist layer (70S) having openings (71S) can be formed on the fourth conductor layer (158S) and the fourth resin insulating layer (150S). The fourth conductor layer (158S) exposed from the openings (71S) forms second pads (73S) for connecting to a wiring board such as a motherboard.

A first solder resist layer (70F) having openings (71F) can be formed on the third resin insulating layer (150F) and the third conductor layer (158F). The third conductor layer (158F) exposed from the openings (71F) forms first pads (73F) for mounting an electronic component. Examples of the electronic component to be mounted on the first pads (73F) include an LED and a power semiconductor, for which a heat generation amount is large when driven.

A method for connection between the first electronic components (32P), the second electronic components (32N), the first conductor circuit (58FW), the for-first-electrode first via conductors (60F1), the for-third-electrode first via conductors (60F3), the second conductor circuit (58SW), the for-second-electrode second via conductors (60S2) and the for-fourth-electrode second via conductors (60S4) is schematically illustrated in FIGS. 6B, 8A, and 8B. FIG. 6B is a cross-sectional view. As illustrated in these drawings, the first electronic components (32P) and the second electronic components (32N) are connected in series via the first conductor circuit (58FW), the for-first-electrode first via conductors (60F1), the for-third-electrode first via conductors (60F3), the second conductor circuit (58SW), the for-second-electrode second via conductors (60S2) and the for-fourth-electrode second via conductors (60S4). The first electronic components (32P) and the second electronic components (32N) are alternately connected. The first electronic components (32P) and the second electronic components (32N) are alternately arranged and connected in series. Connections between the first electronic components (32P) and the second electronic components (32N) via the first conductor circuit (58FW) and connections between the first electronic components (32P) and the second electronic components (32N) via the second conductor circuit (58SW) are alternately repeated.

As illustrated in FIG. 1A, the second pads (73S) include second pads (plus pads) (73SP) having a plus electric potential and second pads (minus pads) (73SN) having a minus electric potential. And, the multiple first electronic components (32P) and the multiple second electronic components (32N) are arranged between the plus pads (73SP) and the minus pads (73 SN). Wirings (for-built-in-component wirings) from the plus pads (73SP) to the minus pads (73 SN) via the first electronic components (32P) and the second electronic components (32N) are independent in the printed wiring board 10. The for-built-in-component wirings include the first conductor circuit (58FW), the for-first-electrode first via conductors (60F1), the for-third-electrode first via conductors (60F3), the second conductor circuit (58SW), the for-second-electrode second via conductors (60S2), and the for-fourth-electrode second via conductors (60S4). The for-built-in-component wirings are not connected to conductor circuits in the printed wiring board other than the for-built-in-component wirings. Data transmitted in the printed wiring board 10 is unlikely to deteriorate. Through-hole conductors (36S) surrounding the opening 31 are included in the for-built-in-component wirings. For example, the number of the through-hole conductors (36S) included in the for-built-in-component wirings is 2. A first conductor circuit (58FWLU) at upper left of FIG. 8A extends from a position above the opening 31 to a position above the core material (20z) and connects to a through-hole conductor (36S). A first conductor circuit (58FWLL) at lower left of FIG. 8A extends from a position above the opening 31 to a position above the core material (20z) and connects to a through-hole conductor (36S).

Second pads having an electric potential lower than that of the plus pads are included in the minus pads.

The first electronic components (32P) and the second electronic components (32N) are connected to the first conductor circuit (58FW) via the first via conductors (60F). Therefore, even when the first electronic components (32P) and the second electronic components (32N) are embedded in the core substrate, heat can be transmitted to the first electronic components (32P) and the second electronic components (32N) via the first conductor circuit (58FW). Heat can be efficiently transmitted to the first electronic components (32P) and the second electronic components (32N). Temperature rise of an electronic component mounted on the printed wiring board can be suppressed. For example, heat is generated from an electronic component mounted on the first pads (73F). In a cross-sectional direction, the core substrate 30 is positioned substantially at a center of the printed wiring board. The cross-sectional direction is perpendicular to the fifth surface (F).

The first electronic components (32P) and the second electronic components (32N) are connected to the second conductor circuit (58SW) via the second via conductors (60S). Therefore, even when the first electronic components (32P) and the second electronic components (32N) are embedded in the core substrate, heat can be transmitted to outside via the second conductor circuit (58SW). Heat can be efficiently transmitted to the outside. For example, heat can be transmitted to a motherboard. Temperature rise of an electronic component mounted on the printed wiring board can be suppressed.

The core material (20z) is formed of a resin such as an epoxy resin and a reinforcing material such as a glass cloth. The core material (20z) may further contain inorganic particles such as silica particles. The first resin insulating layer (50F), the second resin insulating layer (50S), the third resin insulating layer (150F), and the fourth resin insulating layer (150S) are each formed of a resin such as an epoxy resin and inorganic particles such as silica particles. The first resin insulating layer (50F), the second resin insulating layer (50S), the third resin insulating layer (150F), and the fourth resin insulating layer (150S) may each further contain a reinforcing material such as glass cloth.

In the printed wiring board 10 of the first embodiment, heat from an electronic component mounted on the first pads (73F) can be transmitted to a wiring board via the second pads (73S) by applying an electric current to the first electronic components (32P) and the second electronic components (32N).

FIG. 2B illustrates an arrangement of the first electronic components (32P) and the second electronic components (32N) accommodated in the opening 31 of the core substrate 30. The first electronic components (32P) and the second electronic components (32N) are alternately arranged. Each of the second electronic components (32N) is positioned adjacent to one of the first electronic components (32P). As illustrated in FIG. 2B, on the drawing, an electronic component positioned above a first electronic component (32P) is a second electronic component (32N), an electronic component positioned below a first electronic component (32P) is a second electronic component (32N), an electronic component positioned on a right side of a first electronic component (32P) is a second electronic component (32N), and an electronic component positioned on a left side of a first electronic component (32P) is a second electronic component (32N). An electronic component positioned above a second electronic component (32N) is a first electronic component (32P), an electronic component positioned below a second electronic component (32N) is a first electronic component (32P), an electronic component positioned on a right side of a second electronic component (32N) is a first electronic component (32P), and an electronic component positioned on a left side of a second electronic component (32N) is a first electronic component (32P).

The number of the first electronic components (32P) and the number of the second electronic components (32N) accommodated in the one opening 31 are equal to each other.

Multiple kinds of electronic components are embedded in the one opening 31. Examples of the electronic components are the first electronic components (32P) and the second electronic components (32N). Further, the number of the electronic components of each kind is 2 or more. The core substrate 30 is not present between adjacent electronic components. The core material (20z) is not present between adjacent electronic components. Therefore, a size of the opening 31 for accommodating the electronic components can be reduced. A size of the printed wiring board 10 can be reduced. The number of the first electronic components (32P) is 10 or more, and the number of the second electronic components (32N) is 10 or more.

For example, the first electronic components (32P) and the second electronic components (32N) each have a cubical shape. An example of a length of each side is 1 mm.

As illustrated in FIG. 2B, a space (se) exists between a first electronic component (32P) and a second electronic component (32N) which are adjacent to each other. The spaces (se) each have a width (seD) of 10 μm or more and 50 μm or less. Due to the existence of the spaces (se), interference between the first electronic components (32P) and the second electronic components (32N) can be suppressed.

As illustrated in FIG. 2B, a space (sw) exists between the core substrate 30 and a first electronic component (32P). The space (sw) exists between the core substrate 30 and a second electronic component (32N). The space (sw) has a width (swD) of 15 μm or more and 50 μm or less. Due to the existence of the space (sw), interference between the first electronic components (32P) and the fifth conductor layer (34F) can be suppressed. Interference between the second electronic components (32N) and the fifth conductor layer (34F) can be suppressed. Interference between the first electronic components (32P) and the sixth conductor layer (34S) can be suppressed. Interference between the second electronic components (32N) and the sixth conductor layer (34S) can be suppressed.

According to the printed wiring board 10 of the first embodiment, the multiple electronic components (the first electronic component (32P) and the second electronic components (32N)) 32 are accommodated in the one opening 31. Even when a large number of electronic components are embedded in the printed wiring board 10, the size of the printed wiring board 10 can be reduced. Even when the multiple electronic components are embedded in the printed wiring board, the printed wiring board 10 having a small size and a high cooling effect can be provided.

The spaces (se) and the spaces (sw) are filled with the resin 53 originating from the first resin insulating layer (50F). Therefore, the resin 53 formed in the opening 31 and the first resin insulating layer (50F) are integrally formed. An interface between the resin 53 and the first resin insulating layer (50F) is not formed. Therefore, even when the electronic components 32 in the opening 31 are subjected to repeated thermal expansion and thermal contraction, peeling does not occur between the resin 53 and the first resin insulating layer (50F). A highly reliable printed wiring board 10 can be provided. Since the sizes (seD, swD) of the spaces (se) and the spaces (sw) are in appropriate ranges, the resin 53 originating from the first resin insulating layer (50F) can enter into the spaces (se, sw). The spaces (se, sw) can be filled with the resin 53 originating from the first resin insulating layer (50F).

The first wirings (58fW) connect to each other only electronic components of different kinds. The second wirings (58sW) connect to each other only electronic components of different kinds. Interference between electronic components of the same kind can be suppressed. For example, each of the electronic components can exert its maximum capacity. The heat dissipation effect can be increased.

Manufacturing Method of First Embodiment

FIGS. 3A-5B illustrate a method for manufacturing the printed wiring board of the first embodiment.

A double-sided copper-clad laminated plate 20 is prepared (FIG. 3A). The double-sided copper-clad laminated plate 20 is formed of the core material (20z) having the fifth surface (F) and the sixth surface (S) on an opposite side with respect to the fifth surface (F) and a copper foil 22 laminated on both sides of the core material (20z).

Through holes for through-hole conductors are formed in the double-sided copper-clad laminated plate 20. The through-hole conductors 36 are formed in the through holes for through-hole conductors. After that, using a subtractive method, the fifth conductor layer (34F) is formed on the fifth surface (F) of the core material (20z). The sixth conductor layer (34S) is formed on the sixth surface (S) of the core material (20z). The fifth conductor layer (34F) and the sixth conductor layer (34S) are connected to each other by the through-hole conductors 36. A circuit substrate is completed. The fifth conductor layer (34F) has an alignment mark (TM). Using the alignment mark (TM) as a reference, the opening 31 penetrating the circuit substrate is formed at a center part of the circuit substrate. The core substrate 30 having the fifth surface (F) and the sixth surface (S) on an opposite side with respect to the fifth surface (F) is completed (FIG. 3B). The core substrate 30 has the fifth conductor layer (34F), the sixth conductor layer (34S), the through-hole conductors 36, and the opening 31. The fifth surface (F) of the core substrate 30 and the fifth surface (F) of the core material (20z) are the same surface, and the sixth surface (S) of the core substrate 30 and the sixth surface (S) of the core material (20z) are the same surface.

A tape 18 is pasted on the sixth surface (S) of the core substrate 30, and the opening 31 is closed (FIG. 3C). Using the alignment mark (TM) as a reference, first, the first electronic components (32P) are mounted one by one on the tape exposed from the opening 31. The first electronic components (32P) are placed on the tape from the fifth surface (F) side. In this case, as illustrated in FIG. 2A, the first electronic components (32P) are mounted on the tape 18 such that the first electronic components (32P) and spaces (SP) for mounting the second electronic components (32N) are adjacent to each other (FIG. 3D). The first electronic components (32P) are arranged in rows and columns, and the first electronic components (32P) and the spaces (SP) are alternately arranged. The accommodation of the first electronic components (32P) is completed. All the first electronic components (32P) accommodated in the one opening 31 are amounted on the tape 18. After that, using the alignment mark (TM) as a reference, the second electronic components are mounted one by one on the tape exposed from the opening 31 and the first electronic components (32P). The second electronic components (32N) are placed on the tape from the fifth surface (F) side. In this case, as illustrated in FIG. 2B, the second electronic components (32N) are placed in the spaces (SP). The first electronic components (32P) and the second electronic components (32N) are adjacent to each other. The second electronic components (32N) are arranged in rows and columns, and the first electronic components (32P) and the second electronic components (32N) are alternately arranged (FIG. 4A). As illustrated in FIG. 2C, the first electronic components (32P) and the second electronic components (32N) are arranged at intersection points of rows and columns. The number of the rows and the number of the columns are the same. The number of the rows is 4 or more, and the number of the columns is 4 or more. In the method for manufacturing the printed wiring board of the first embodiment, first, all the first electronic components (32P) are accommodated in the opening 31. After that, all the second electronic components (32N) are accommodated in the opening 31. Therefore, the two kinds of electronic components (32P, 32N) can be accommodated at correct positions. The formation of the opening 31 and the mounting of the electronic components (32P, 32N) are performed using the same alignment mark (TM) as a reference. Therefore, positional accuracy between the opening 31 and the electronic components (32P, 32N) can be increased. Positional accuracy between the first electronic components (32P) and the second electronic components (32N) can be increased. The width (seD) of each of the spaces (se) can be set in a predetermined range (10 μm or more and 50 μm or less). The width (swD) of each of the spaces (sw) can be set in a predetermined range (15 μm or more and 50 μm or less).

A mounting order of the first electronic components (32P) and the second electronic components (32N) is arbitrary.

When the electronic components (32P, 32N) are mounted on the tape 18, an uncured film for resin insulating layer formation is laminated on the fifth surface (F) of the core substrate 30. In this case, the film for resin insulating layer formation covers the opening 31. After that, by hot pressing, the film for resin insulating layer formation is softened. The spaces (se) and the spaces (sw) are filled with a resin containing inorganic particles originating from the film for resin insulating layer formation (FIG. 4B). The film for resin insulating layer formation, the resin filled in the spaces (se), and the resin filled in the spaces (sw) are cured. The first resin insulating layer (50F) is formed on the core substrate 30 and the opening 31. The resin 53 filled in the spaces (se) and the spaces (sw) is formed. The first resin insulating layer (50F) and the resin 53 are integrally formed.

The first resin insulating layer (50F) has a bottom surface (BF) opposing the fifth surface (F) and a top surface (TF) on an opposite side with respect to the bottom surface (BF).

The tape 18 is removed from the core substrate 30. The second resin insulating layer (50S) is formed on the sixth surface (S) of the core substrate 30 and the opening 31 (FIG. 4C).

The second resin insulating layer (50S) has a bottom surface (BS) opposing the sixth surface (S) and a top surface (TS) on an opposite side with respect to the bottom surface (BS).

The first conductor layer (58F) is formed on the first resin insulating layer (50F). At the same time, the first via conductors (60F) penetrating the first resin insulating layer (50F) are formed. The first conductor layer (58F) and the first via conductors (60F) are formed using a semi-additive method. Openings for the first via conductors penetrating the first resin insulating layer (50F) are formed. Then, by filling the openings, the first via conductors (60F) are formed. The openings for the first via conductors each have the top diameter (TDF) at the position of the top surface (TF) of the first resin insulating layer (50F).

The first conductor layer (58F) includes the on-first-electrode first conductor circuits (58FW1) each of which is formed on one first electronic component (32P), and the on-third-electrode first conductor circuits (58FW3) each of which is formed on one second electronic component (32N). The multiple on-first-electrode first conductor circuits (58FW1) and the multiple on-third-electrode first conductor circuits (58FW3) are formed. A first electronic component (32P) and a second electronic component (32N), which are adjacent to each other, are connected to each other by one first wiring (58fW). One first electronic component (32P) and one second electronic component (32N) are connected to each other by one first wiring (58fW).

The first via conductors (60F) include the for-fifth-conductor-layer first via conductors (60F5) that connect the first conductor layer (58F) to the fifth conductor layer (34F), the for-first-electrode first via conductors (60F1) that connect the first electrodes (32P1) to the first conductor circuit (58FW), and the for-third-electrode first via conductors (60F3) that connect the third electrodes (32P3) to the first conductor circuit (58FW). The for-fifth-conductor-layer first via conductors (60F5) each have the top diameter (TDF) at the position of the top surface (TF). The for-first-electrode first via conductors (60F1) each have the top diameter (TDF) at the position of the top surface (TF). The for-third-electrode first via conductors (60F3) each have the top diameter (TDF) at the position of the top surface (TF). The top diameter (TDF) of each of the for-fifth-conductor-layer first via conductors (60F5), the top diameter (TDF) of each of the for-first-electrode first via conductors (60F1), and the top diameter (TDF) of each of the for-third-electrode first via conductors (60F3) are substantially equal to each other. The for-first-electrode first via conductors (60F1) and the for-third-electrode first via conductors (60F3) are formed using the alignment mark (TM) as a reference.

One first electrode (32P1) is connected to the first conductor circuit (58FW) by multiple for-first-electrode first via conductors (60F1). For example, the number of the for-first-electrode first via conductors (60F1) connecting one first electrode (32P1) to the first conductor circuit (58FW) is 30 or more and 40 or less.

One third electrode (32P3) is connected to the first conductor circuit (58FW) by multiple for-third-electrode first via conductors (60F3). For example, the number of the for-third-electrode first via conductors (60F3) connecting one third electrode (32P3)) to the first conductor circuit (58FW) is 30 or more and 40 or less.

The second conductor layer (58S) is formed on the second resin insulating layer (50S). At the same time, the second via conductors (60S) penetrating the second resin insulating layer (50S) are formed. The second conductor layer (58S) and the second via conductors (60S) are fanned using a semi-additive method. Openings for the second via conductors penetrating the second resin insulating layer (50S) are formed. Then, by filling the openings, the second via conductors (60S) are formed. The openings for the second via conductors each have the top diameter (TDS) at the position of the top surface (TS) of the second resin insulating layer (50S).

The second conductor layer (58S) includes the on-second-electrode second conductor circuits (58SW2) each of which is formed on one first electronic component (32P), and the on-fourth-electrode second conductor circuits (58SW4) each of which is formed on one second electronic component (32N). The multiple on-second-electrode second conductor circuits (58SW2) and the multiple on-fourth-electrode second conductor circuits (58SW4) are formed. A first electronic component (32P) and a second electronic component (32N), which are adjacent to each other, are connected to each other by one second wiring (58sW). One first electronic component (32P) and one second electronic component (32N) are connected to each other by one second wiring (58sW).

The second via conductors (60S) include the for-sixth-conductor-layer second via conductors (60S6) that connect the second conductor layer (58S) to the sixth conductor layer (34S), the for-second-electrode second via conductors (60S2) that connect the second electrodes (32P2) to the second conductor circuit (58SW), and the for-fourth-electrode second via conductors (60S4) that connect the fourth electrodes (32P4) to the second conductor circuit (58SW). The for-sixth-conductor-layer second via conductors (60S6) each have the top diameter (TDS) at the position of the top surface (TS). The for-second-electrode second via conductors (60S2) each have the top diameter (TDS) at the position of the top surface (TS). The for-fourth-electrode second via conductors (60S4) each have the top diameter (TDS) at the position of the top surface (TS). The top diameter (TDS) of each of the for-sixth-conductor-layer second via conductors (60S6), the top diameter (TDS) of each of the for-second-electrode second via conductors (60S2) and the top diameter (TDS) of each of the for-fourth-electrode second via conductors (60S4) are substantially equal to each other.

One second electrode (32P2) is connected to the second conductor circuit (58SW) by multiple for-second-electrode second via conductors (60S2). For example, the number of the for-second-electrode second via conductors (60S2) connecting one second electrode (32P2) to the second conductor circuit (58SW) is 30 or more and 40 or less.

One fourth electrode (32P4) is connected to the second conductor circuit (58SW) by multiple for-fourth-electrode second via conductors (60S4). For example, the number of the for-fourth-electrode second via conductors (60S4) connecting one fourth electrode (32P4) to the second conductor circuit (58SW) is 30 or more and 40 or less (FIG. 5A).

The third resin insulating layer (150F) is formed on the first conductor layer (58F) and the first resin insulating layer (50F). The third conductor layer (158F) is formed on the third resin insulating layer (150F) using a semi-additive method. At the same time, the third via conductors (160F) penetrating the third resin insulating layer (150F) and connecting the first conductor layer (58F) and the third conductor layer (158F) to each other are formed (FIG. 5B). For example, there is no third via conductor (160F) that connects the third conductor layer (158F) and the first conductor circuit (58FW) to each other.

The fourth resin insulating layer (150S) is formed on the second conductor layer (58S) and the second resin insulating layer (50S). The fourth conductor layer (158S) is formed on the fourth resin insulating layer (150S) using a semi-additive method. At the same time, the fourth via conductors (160S) penetrating the fourth resin insulating layer (150S) and connecting the second conductor layer (58S) and the fourth conductor layer (158S) to each other are formed (FIG. 5B). For example, there is no fourth via conductors (160S) that connects the fourth conductor layer (158S) and the second conductor circuit (58SW) to each other.

The first solder resist layer (70F) having the first openings (71F) are formed on the third conductor layer (158F) and the third resin insulating layer (150F). The second solder resist layer (70S) having second openings (71S) are formed on the fourth conductor layer (158S) and the fourth resin insulating layer (150S). The printed wiring board 10 is completed (FIG. 1A). The third conductor layer (158F) exposed from the first openings (71F) functions as the pads for mounting an electronic component. The fourth conductor layer (158S) exposed from the second openings (71S) functions as the pads for connecting to a motherboard.

Second Embodiment

FIG. 6A is a cross-sectional view of a printed wiring board 110 of a second embodiment. In the printed wiring board 110, three kinds of electronic components 33 are accommodated in the opening 31 of the core substrate 30. Examples of the electronic components 33 accommodated in the one opening 31 are capacitors (33C), inductors (33L) and resistors (33R).

Manufacturing Method of Second Embodiment

FIGS. 7A-7C illustrate a part of a method for manufacturing the printed wiring board 110 of the second embodiment. FIGS. 7A-7C illustrate a method in which the electronic components 33 are mounted on the tape 18 which closes the opening 31.

Similar to the first embodiment, using the alignment mark (TM) as a reference, first, first electronic components such as the capacitors (33C) are mounted one by one on the tape 18 in the opening 31. The accommodation of the first electronic components such as the capacitors (33C) is completed. As illustrated in FIG. 7A, all the first electronic components such as the capacitors (33C) are mounted on the tape 18 exposed from the opening 31. After that, using the alignment mark (TM) as a reference, second electronic components such as the inductors (33L) are mounted one by one on the tape 18. The accommodation of the second electronic components such as the inductors (33L) is completed. All the second electronic components such as the inductors (33L) are mounted on the tape 18 exposed from the opening 31. Finally, using the alignment mark (TM) as a reference, third electronic components such as the resistors (33R) are mounted one by one on the tape 18. The accommodation of the third electronic components such as the resistors (33R) is completed. All the third electronic components such as the resistors (33R) are accommodated on the tape 18 exposed from the opening 31. The three kinds of electronic components 33 are arranged at intersection points of rows and columns.

A method for forming the core substrate 30 of the first embodiment and a method for forming the core substrate 30 of the second embodiment are the same. A method for forming the first build-up layer (55F) of the first embodiment and a method for forming the first build-up layer (55F) of the second embodiment are the same. A method for forming the second build-up layer (55S) of the first embodiment and a method for forming the second build-up layer (55S) of the second embodiment are the same. A method for forming the first solder resist layer (70F) of the first embodiment and a method for forming the first solder resist layer (70F) of the second embodiment are the same. A method for forming the second solder resist layer (70S) of the first embodiment and a method for forming the second solder resist layer (70S) of the second embodiment are the same.

A row is substantially parallel to a side wall of the core substrate exposed from the opening 31 for accommodating the electronic components 32. A column is substantially parallel to the side wall of the core substrate exposed from the opening 31 for accommodating the electronic components 32.

The first conductor circuit (58FW) can include a first conductor circuit (58FWF1) that connects the first electronic components (32P) to the through-hole conductors (36S) (the through-hole conductors among the for-built-in-component wirings) in FIG. 1A, and a first conductor circuit (58FWF2) that connect the second electronic components (32N) to the through-hole conductors (36S) (the through-hole conductors among the for-built-in-component wirings) in FIG. 1A.

The second conductor circuit (58SW) can include a second conductor circuit that connects the first electronic components (32P) to the through-hole conductors among the for-built-in-component wirings, and a second conductor circuit that connects the second electronic components (32N) to the through-hole conductors (36S) among the for-built-in-component wirings.

FIG. 6C illustrates two first electronic components (32P) (32P1, 32P11) and two second electronic components (32N) (32N1, 32N11) arranged in one row. As illustrated in FIG. 6C, the electronic components are arranged in an order of the first electronic component (32P1), the second electronic component (32N1), the first electronic component (32P11), and the second electronic component (32N11). A straight line (L2) connecting a centroid of the first surface (F1) of the first electronic component (32P1) and a centroid of the first surface (F1) of the first electronic component (32P11) is illustrated in FIG. 6C. A straight line (L1) connecting a centroid of the third surface (F2) of the second electronic component (32N1) and a centroid of the third surface (F2) of the second electronic component (32N11) is illustrated in FIG. 6C. The straight line (L1) and the straight line (L2) do not overlap each other. There is a gap between the straight line (L1) and the straight line (L2). Heat conduction can be increased.

A straight line connecting a centroid of the first surface of one first electronic component arranged on a specific row and a centroid of the first surface of another first electronic component arranged on the specific row and a straight line connecting a centroid of the third surface of one second electronic component arranged on the specific row and a centroid of the third surface of another second electronic component arranged on the specific row do not overlap each other.

FIG. 6D illustrates two first electronic components (32P) (32P1, 32P11) and two second electronic components (32N) (32N1, 32N11) arranged in one column. As illustrated in FIG. 6D, the electronic components are arranged in an order of the first electronic component (32P1), the second electronic component (32N1), the first electronic component (32P11), and the second electronic component (32N11). A straight line (L4) connecting a centroid of the first surface (F1) of the first electronic component (32P1) and a centroid of the first surface (F1) of the first electronic component (32P11) is illustrated in FIG. 6D. A straight line (L3) connecting a centroid of the third surface (F2) of the second electronic component (32N1) and a centroid of the third surface (F2) of the second electronic component (32NII) is illustrated in FIG. 6D. The straight line (L3) and the straight line (L4) do not overlap each other. There is a gap between the straight line (L3) and the straight line (L4). Heat conduction can be increased.

A straight line connecting a centroid of the first surface of one first electronic component arranged on a specific column and a centroid of the first surface of another first electronic component arranged on the specific column and a straight line connecting a centroid of the third surface of one second electronic component arranged on the specific column and a centroid of the third surface of another second electronic component arranged on the specific column do not overlap each other.

According to an embodiment, temperature of an electronic component mounted on the printed wiring board can be controlled within a predetermined range.

In Japanese Patent Laid-Open Publication No. 2012-039050, through holes are formed in a metal substrate. And, in Japanese Patent Laid-Open Publication No. 2012-039050, one semiconductor element is accommodated in each of the through holes. Therefore, according to Japanese Patent Laid-Open Publication No. 2012-039050, it is expected that, when the number of the semiconductor elements embedded in the metal substrate increases, the substrate becomes large.

A method for manufacturing a printed wiring board according to an embodiment of the present invention includes: preparing a circuit substrate having a fifth surface and a sixth surface on an opposite side with respect to the fifth surface; forming a core substrate by foil ling an opening, in the circuit substrate, for accommodating electronic components; pasting a tape for closing the opening on the sixth surface of the core substrate; mounting multiple first electronic components on the tape exposed from the opening; mounting multiple second electronic components on the tape exposed from the opening and the first electronic components; filling spaces between the first electronic components and the second electronic components, spaces between the first electronic components and the core substrate, and spaces between the second electronic components and the core substrate with a resin; and removing the tape from the core substrate.

According an embodiment of the present invention, the multiple first electronic components and the multiple second electronic components are accommodated in the one opening. Therefore, it is possible that the core substrate is not formed between the first electronic components and the second electronic components. The printed wiring board can be reduced in size. Further, all the first electronic components can be first mounted on the tape exposed from the opening. After that, all the second electronic components can be mounted on the tape exposed from the opening and the first electronic components. Therefore, multiple kinds of electronic components can be accommodated in the opening with high accuracy.

Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.

Claims

1. A method for manufacturing a printed wiring board, comprising: forming an opening through a core substrate such that the opening is configured to accommodate a plurality of first electronic components and a plurality of second electronic components;pasting a tape on a surface of the core substrate such that the tape closes the opening of the core substrate on one side;mounting the plurality of first electronic components on the tape exposed in the opening of the core substrate such that the plurality of first electronic components is positioned inside the opening of the core substrate;mounting the plurality of second electronic components on the tape exposed in the opening of the core substrate such that the plurality of second electronic components is positioned inside the opening of the core substrate;filling resin in spaces formed between the first electronic components and the second electronic components, spaces between the first electronic components and the core substrate, and spaces between the second electronic components and the core substrate; andremoving the tape from the core substrate.

2. The method for manufacturing a printed wiring board according to claim 1, wherein the mounting of the first electronic components comprises completing the mounting of the first electronic components before the mounting of the second electronic components.

3. The method for manufacturing a printed wiring board according to claim 1, wherein the mounting of the first electronic components comprises positioning the first electronic components on the tape such that each of the second electronic components is mounted between adjacent ones of the first electronic components.

4. The method for manufacturing a printed wiring board according to claim 1, wherein the first electronic components and the second electronic components are alternately positioned.

5. The method for manufacturing a printed wiring board according to claim 1, wherein the mounting of the first electronic components and the mounting of the second electronic components comprise mounting equal numbers of the first electronic components and the second electronic components in the opening of the core substrate.

6. The method for manufacturing a printed wiring board according to claim 1, wherein each of the first electronic components is an N-type thermoelectric element or a P-type thermoelectric element.

7. The method for manufacturing a printed wiring board according to claim 1, wherein each of the first electronic components is a P-type thermoelectric element, and each of the second electronic components is an N-type thermoelectric element.

8. The method for manufacturing a printed wiring board according to claim 1, wherein the mounting of the first electronic components and the mounting of the second electronic components comprise placing the first electronic components and the second electronic components at intersection points of rows and columns such that the first electronic components and the second electronic components are alternately positioned.

9. The method for manufacturing a printed wiring board according to claim 8, wherein a number of the rows is equal to a number of the columns.

10. The method for manufacturing a printed wiring board according to claim 8, wherein a number of the rows is 4 or more, and a number of the columns is 4 or more.

11. The method for manufacturing a printed wiring board according to claim 2, wherein the mounting of the first electronic components comprises positioning the first electronic components on the tape such that each of the second electronic components is mounted between adjacent ones of the first electronic components.

12. The method for manufacturing a printed wiring board according to claim 2, wherein the first electronic components and the second electronic components are alternately positioned.

13. The method for manufacturing a printed wiring board according to claim 2, wherein the mounting of the first electronic components and the mounting of the second electronic components comprise mounting equal numbers of the first electronic components and the second electronic components in the opening of the core substrate.

14. The method for manufacturing a printed wiring board according to claim 2, wherein each of the first electronic components is an N-type thermoelectric element or a P-type thermoelectric element.

15. The method for manufacturing a printed wiring board according to claim 2, wherein each of the first electronic components is a P-type thermoelectric element, and each of the second electronic components is an N-type thermoelectric element.

16. The method for manufacturing a printed wiring board according to claim 2, wherein the mounting of the first electronic components and the mounting of the second electronic components comprise placing the first electronic components and the second electronic components at intersection points of rows and columns such that the first electronic components and the second electronic components are alternately positioned.

17. The method for manufacturing a printed wiring board according to claim 16, wherein a number of the rows is equal to a number of the columns.

18. The method for manufacturing a printed wiring board according to claim 16, wherein a number of the rows is 4 or more, and a number of the columns is 4 or more.

19. The method for manufacturing a printed wiring board according to claim 3, wherein each of the first electronic components is an N-type thermoelectric element or a P-type thermoelectric element.

20. The method for manufacturing a printed wiring board according to claim 3, wherein each of the first electronic components is a P-type thermoelectric element, and each of the second electronic components is an N-type thermoelectric element.