Patent Grant
7364971
The present invention relates to a semiconductor device having a super junction construction and a method for manufacturing the same.
A vertical type MOSFET (i.e., metal-oxide semiconductor field effect transistor) having a trench gate electrode has low on-state resistance and high withstand voltage. Therefore, the vertical type MOSFET is suitably used for a switching device in power electronic equipment. When the on-state resistance and the withstand voltage are improved much more, a relationship between the on-state resistance and the withstand voltage shows a trade-off relationship. Specifically, when the on-state resistance is reduced, the withstand voltage decreases. When the withstand voltage is increased, the on-state resistance increases.
In view of the above trade-off relationship, a vertical type MOSFET having a trench gate electrode with a super junction construction is disclosed in Japanese Patent Application Publications No. H09-266311 (i.e., U.S. Pat. No. 6,294,818) and No. 2000-260984.
As shown in
When the trench gate electrode 36 of the semiconductor device 1 is applied with positive voltage, an inversion layer is formed in the body region 30 having the P type conductivity, which faces a side of the trench gate electrode 36. The inversion layer of the body region 30 becomes a channel. Therefore, electrons supplied to the source region 32 from the source power supply S pass through the channel of the body region 30 and the N type column 26, and then, flows toward the N type drain region 22.
When the trench gate electrode 36 is grounded, no inversion layer is formed in the P type body region 30 facing the side of the trench gate electrode 36. Therefore, the semiconductor device 1 becomes off state. When the source voltage and the gate voltage are set to be zero Volts, and an inversion bias voltage is applied to the semiconductor device 1, a depletion layer extends in the P type column 24 and the N type column 26 from a P-N junction surface between the P type column 24 and the N type column 26. Here, the drain voltage is set to be a positive voltage. At this time, each impurity concentration of the P type column 24 and the N type column 26 and a column width (i.e., a pitch in the repeat direction) of them are disposed in an appropriate range, the depletion layer expands uniformly in the whole area of the P type column 24 and the N type column 26, so that the whole area of them is completely depleted substantially. Thus, the off state withstand voltage becomes high.
The on state resistance of the semiconductor device 1 is the sum of a channel resistance, a drift resistance and a resistance of the N type drain region 22. The channel resistance is a resistance of the channel formed around the trench gate electrode 36. Specifically, the channel resistance is the resistance of the channel of the body region 30. The drift resistance is a resistance of the N type column 26. In the vertical type MOSFET shown in
When the impurity concentration of the N type column 26 is increased, the impurity concentration of the P type column 24 is required to be increased. This is because the depletion layer expanding in the P type column 24 and the N type column 26 from the P-N junction surface may become imbalanced if the impurity concentration of the P type column 24 is not increased. Therefore, to deplete the drift region 23 completely, the column width of the N type column 26 is required to be smaller than that of the P type column 24. Each column width is defined by a pitch in the repeat direction. However, if the column width of the N type column 26 becomes small, a cross sectional area of the N type column 26 is reduced, so that it is difficult to reduce the resistance of the N type column 26.
Therefore, it is required that the impurity concentration of the P type column 24 is increased in accordance with increase of the impurity concentration of the N type column 26, and the column width of the P type column 24 is equalized to that of the N type column 26.
In the semiconductor device 1 shown in
Another semiconductor device is disclosed in Japanese Patent Application Publication No. 2000-260984. In the semiconductor device, the impurity concentration of the N type column 26 is increased so that the resistance of the drift region 23 is reduced. Further, the inversion layer (i.e., the channel) formed in the body region 30 is effectively used for reducing the channel resistance. The semiconductor device includes an N type channel region disposed between the drift region 23 and the body region 30 in the super junction construction.
The N type channel region provides the current path between the inversion region disposed on the P type column 24 and the N type column 26 through the N type channel region. In this case, the inversion layer of the body region 30 facing the trench gate electrode 36, specifically, the inversion layer disposed on the P type column 24 can flow the current. Here, the inversion layer disposed on the P type column 24 in the semiconductor device 1 shown in
In the semiconductor device, the impurity concentration of the N type column 26 is increased so that the drift resistance is reduced. Further, the N type channel region provides to reduce the channel resistance. However, the semiconductor device necessitates the N type channel region. Further, a method for manufacturing the semiconductor device necessitates an additional process for forming the N type channel region.
Furthermore, the N type channel region causes a floating of electric potential in the P type column 24. When the potential of the P type column 24 is unstable, the P-N junction surface between the P type column 24 and the N type column 26 is not applied with sufficient voltage, so that the P type and N type columns 24, 26 may not be depleted. Thus, the withstand voltage is unstable.
In view of the above-described problem, it is an object of the present invention to provide a semiconductor device having low on state resistance without increasing an additional process for forming an additional part.
A semiconductor device includes: a body region having a first conductive type; a drift region including a first part and a second part; and a trench gate electrode. The body region is disposed on the drift region. The first part of the drift region has the first conductive type, and extends in an extending direction. The second part of the drift region has the second conductive type, is disposed adjacent to the first part of the drift region, and extends in the extending direction. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part of the drift region includes a portion near the trench gate electrode. The portion of the first part has an impurity concentration, which is equal to or lower than that of the body region.
In the above semiconductor device, the impurity concentration of the portion of the first part is lower than that of the body region, so that the on state resistance is reduced. This is because the channel resistance in the device is much reduced so that the total on state resistance is decreased. Thus, the channel resistance is reduced without increasing an additional part such as the N type channel region. Therefore, the manufacturing cost of the semiconductor device becomes lower. Further, since the device does not have the N type channel region, the potential of the first part is prevented from floating so that the potential of the first part is stable. Thus, the withstand voltage is also stable.
Preferably, the first part of the drift region except for the portion near the trench gate electrode has another impurity concentration, which is equal to or higher than that of the body region.
Preferably, the portion of the first part is the whole first part so that the impurity concentration of the whole first part is equal to or lower than that of the body region.
Preferably, the device further includes a plurality of trench gate electrodes aligned in parallel together. The trench gate electrodes are disposed separately so that the body region is sandwiched between two trench gate electrodes.
Further, a method for manufacturing a semiconductor device includes the steps of: forming a plurality of second parts having a second conductive type, wherein each second part is disposed separately; forming a plurality of first parts having a first conductive type, wherein each first part is disposed between two second parts so that a drift region including the first and second parts aligned alternately in a repeat direction is provided; forming a body region having the first conductive type on the drift region; forming a trench, which penetrates the body region and reaches the drift region, wherein the trench extends in parallel to the repeat direction; forming an insulation film on an inner wall of the trench; and embedding a gate electrode in the trench through the insulation film.
The above method provides a semiconductor device having a small on state resistance. Further, the manufacturing cost of the semiconductor device becomes lower. Further, since the device does not have the N type channel region, the potential of the first part is prevented from floating so that the potential of the first part is stable. Thus, the withstand voltage is also stable.
Preferably, the method further includes the step of reducing an impurity concentration of a portion of the first part of the drift region so that the impurity concentration of the portion is equal to or lower than that of the body region. The portion of the first part is disposed near the trench gate electrode.
Preferably, the step of forming the first parts is performed by an epitaxial growth method. The step of forming the body region is performed by the epitaxial growth method, which is continuously performed after the step of forming the first parts.
Preferably, the method further includes the steps of: forming a plurality of trenches, which penetrates the body region and reaches the drift region, wherein the trenches extend in parallel to the repeat direction; forming an insulation film on an inner wall of each trench; and embedding a gate electrode in each trench through the insulation film. The trenches are aligned in parallel together, and the trenches are disposed separately so that the body region is sandwiched between two trench gate electrodes.
Furthermore, a method for manufacturing a semiconductor device includes the steps of: forming a plurality of second parts having a second conductive type, wherein each second part is disposed separately; forming a plurality of first parts having a first conductive type, wherein each first part is disposed between the second parts so that an under drift region including the first and second parts aligned alternately in a repeat direction is provided; forming a semiconductor layer on the under drift region, wherein the semiconductor layer has the first conductive type and an impurity concentration of the semiconductor layer is lower than that of the first part of the under drift region; and doping an impurity having the second conductive type into a part of the semiconductor layer so that the part of the semiconductor layer changes its conductive type from the first conductive type to the second conductive type, wherein the part of the semiconductor layer is disposed on the second part.
The above method provides a semiconductor device having a small on state resistance. Further, the manufacturing cost of the semiconductor device becomes lower. Further, since the device does not have the N type channel region, the potential of the first part is prevented from floating so that the potential of the first part is stable. Thus, the withstand voltage is also stable.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:
A semiconductor device 3 with a vertical type MOSFET having a trench gate electrode according to a first embodiment of the present invention is shown in
The trench gate electrode 36 penetrates through the body region 30, which separates between the source region 32 and the drift region 23. The trench gate electrode 36 extends toward a repeat direction of the P type column 24 and the N type column 26, so that the trench gate electrode 36 penetrates the alternate layer. The trench gate electrode 36 faces a semiconductor region such as the upside of the source region 32, the body region 30 and the drift region 23.
The drain region 22 is made of an N+ type silicon substrate. The drift region 23 has a super junction construction such that the unit of the alternate layer composed of the P type column 24 and the N type column 26 is repeated alternately. A withstand voltage can be controlled by changing a thickness of the alternate layer in a longitudinal direction. When a value obtained by multiplying the width of the P type column 24 in the repeat direction by the impurity concentration of the P type column 24 is almost equal to a value obtained by multiplying the width of the N type column 26 in the repeat direction by the impurity concentration of the N type column 26, the drift region 23 is completely depleted substantially so that the off state withstand voltage is improved. The impurity concentration of the P type column 24 is set to be equal to or smaller than that of the P type body region 30. In the semiconductor device 3 shown in
Here, in
As shown in
As shown in
Thus, the current flows from the N type column 26, and passes through the inversion layer of the body region 30 disposed on the P type column 24 and facing the trench gate electrode 36. Therefore, the whole area of the inversion layer in the body region 30 facing the trench gate electrode 36 works as a channel. Thus, the current path is secured widely.
As described later, when the impurity concentration of the P type column 24 becomes higher than that of the P type body region 30, the upside of the P type column 24 facing the bottom of the trench gate electrode 36 does not flow the current. Further, in this case, the current does not flow in the P type body region 30 facing the side of the trench gate electrode 36 and disposed on the P type column 24.
A longitudinal direction (i.e., an extending direction) of the P type column 24 and the N type column 26 is not parallel to a longitudinal direction (i.e., an extending direction) of the trench gate electrode 36 so that they intersect with each other. Specifically, in the semiconductor device 3, the longitudinal direction of the P type column 24 and the N type column 26 is perpendicular to the longitudinal direction of the trench gate electrode 36. Further, the impurity concentration of the P type column 24 is set to be equal to or smaller than that of the P type body region 30. In this case, a channel is formed in the upside of the P type column 24 adjacent to the bottom of the trench gate electrode 36. Another channel is also formed in the P type body region facing the side of the trench gate electrode 36 and disposed on the P type column 24. Thus, the current flows through the channels so that the channel resistance is reduced. In the present embodiment, the specific on state resistance (i.e., Ron) is 0.157 Ω·mm2.
In the off state of the semiconductor device 3, the depletion layer expands from the P-N junction surface formed between the P type column 24 and the N type column 26 into both of the P type column 24 and the n type column 26. The expansion of the depletion layer depends on the impurity concentration of each of the P or N type column 24, 26. For example, as the impurity concentration of the P or N type column 24, 26 becomes higher, the expansion of the depletion layer becomes small.
In the prior art, the drift resistance of the semiconductor device 1 shown in
In the semiconductor device 3 according to the first embodiment, the impurity concentration of the P type column 24 becomes lower than that of the body region 30, so that the on state resistance is reduced. In this case, it is required to reduce the impurity concentration of the N type column 26 or to narrow the column width of the N type column 26 so that the cross sectional area of the N type column 26 is reduced. Therefore, the drift resistance is not reduced (i.e., increased). However, when the impurity concentration of the P type column 24 becomes lower than that of the body region 30, the channel resistance is much reduced so that the total on state resistance is decreased. This reason is described as follows. In a case where the impurity concentration of the P type column 24 is lower than that of the body region 30, the body region 30 facing the trench gate electrode 36 is reversed, and further, the P type column 24 facing the trench gate electrode 36 is also reversed. The inversion layer of the P type column 24 facing the trench gate electrode 36 is disposed between the inversion layer of the body region 30 facing the trench gate electrode 36 and disposed on the P type column 24 and the N type column 26. When the P type column 24 facing the trench gate electrode 36 is reversed, the inversion layer of the body region 30 facing the trench gate electrode 36 and disposed on the P type column 24 can work as a channel. Thus, the channel resistance is reduced.
Accordingly, in the semiconductor device 3, the channel resistance is reduced without increasing an additional part such as the N type channel region in the semiconductor device according to the prior art. Therefore, the manufacturing cost of the semiconductor device 3 becomes lower. Further, since the device 3 does not have the N type channel region, the potential of the P type column is prevented from floating so that the potential of the P type column is stable. Thus, the withstand voltage is also stable.
Although the body region 30, the body contact region 30a, and the P type column (i.e., the first part) have the P type conductivity, and the source region 32, the N type column (i.e., the second part), and the drain region 22 have the N type conductivity, each part of the device 3 can have inverse type conductivity. Specifically, the body region 30, the body contact region 30a, and the P type column (i.e., the first part) have the N type conductivity, and the source region 32, the N type column (i.e., the second part), and the drain region 22 have the P type conductivity.
Although the impurity concentration of whole area of the P type column 24 is equal to or lower than that of the body region 30, the impurity concentration of at least a part of the P type column 24 can be equal to or lower than that of the body region 30. The part of the P type column 24 is disposed near the trench gate electrode 36. Specifically, the part of the P type column 24 faces the trench gate electrode 36 and has predetermined dimensions, in which the channel is formed.
Preferably, the impurity concentration of the other part of the P type column 24 is lower than that of the body region 30. In this case, since the impurity concentration of the part of the P type column 24 disposed near the trench gate electrode 36 is low, the part of the P type column 24 is reversed so that the inversion layer of the body region 30 facing the trench gate electrode 36 and disposed on the P type column 24 can work as a channel. Thus, the channel resistance is reduced. Further, since the impurity concentration of the other part of the P type column 24 is high, the drift resistance is also reduced. Thus, both of the channel resistance and the drift resistance are reduced.
Although the P type column 24 contacts the N type column 26 directly, the P type column 24 can contact the N type column 26 through an insulation layer. Although the trench gate electrode 36 penetrates the body region 30 and extends inside of the drift region 23, the trench gate electrode 36 is not required to extend inside of the drift region 23 as long as the trench gate electrode 36 reaches the drift region 23.
Although the trench gate electrode 36 extends in parallel to the repeat direction of the P type and N type columns 24, 26, the trench gate electrode 36 can cross the repeat direction with a predetermined angle. Specifically, the trench gate electrode 36 can be cross the repeat direction at a slant.
Although the device 3 includes the source region 32 and the drain region 22, it is not necessary for the device 3 to include the source region 32 and/or the drain region 22. In this case, the device 3 only includes the body region 30, the drift region 23 and the trench gate electrode 36.
As shown in
In the present embodiment, the specific on state resistance (i.e., Ron) is 0.195 Ω·mm2.
Here, another semiconductor device 5 as a comparison of the semiconductor device 4 is shown in
In the comparison device 5, the specific on state resistance (i.e., Ron) is 0.214 Ω·mm2, which is about 36% larger than that in the semiconductor device 3 shown in
Accordingly, it is important to set the impurity concentration of the first part (i.e., the P type column) 24 in the drift region 23 to be equal to or smaller than that of the body region 30.
The on state resistance in the semiconductor devices 3, 4 shown in
When the withstand voltage is low, the depth of the drift region 23 becomes shallow. Thus, the percentage of the drift resistance constituting in the on state resistance is reduced. This shows that the percentage of the channel resistance constituting in the on state resistance is increased. In the semiconductor devices 3, 4, the current path extends in a wide area of the channel so that the channel resistance is reduced. Therefore, when the withstand voltage is low, i.e., when the depth of the drift region 23 in the super junction construction is shallow, the reduction of the on state resistance becomes more effective. Further, in the semiconductor device 4, a floating potential state is prevented from occurring, so that the characteristic of the withstand voltage is stabilized.
When the power MOSFET having the super junction construction is manufactured according to a prior art, a crystal growth process for forming the P type column 24 is performed independently from a crystal growth process for forming the P type body region 30. Here, in general, the P type column 24 is formed by an epitaxial growth method. This is because the impurity concentration of the P type column 24 is different from that of the P type body region 30. Specifically, the impurity concentration of the P type column 24 is determined such that the P type column 24 can be completely depleted substantially. The impurity concentration of the P type body region 30 is determined such that the trench gate electrode 36 has a predetermined threshold voltage.
However, in the semiconductor device 4 shown in
In the above method for performing the process for forming the P type column 24 and the process for forming the P type body region 30 successively, it is preferred that the column width of the P type column 24 is equal to or narrower than 1 μm. In general, to deplete the P type column 24 completely, it is preferred that the value obtained by multiplying the impurity concentration of the P type column 24 by the column width of the P type column 24 is equal to or smaller than 1×1012 cm−3. In this case, the P type column 24 is completely depleted substantially. The impurity concentration of the P type body region 30 is determined by the threshold voltage of the trench gate electrode 36 so that the impurity concentration is set to be in a range between 1×1016 cm−3 and 1×1017 cm−3. Therefore, when the column width of the P type column 24 is equal to or narrower than 1 μm, the impurity concentration of the P type column 24 can be set to be equal to or higher than 1×1016 cm−3. Therefore, the impurity concentration of the P type column 24 can be equalized to that of the P type body region 30. Thus, the process for forming the P type column 24 and the process for forming the P type body region 30 can be performed successively.
A semiconductor device 6 according to a third embodiment of the present invention is shown in
Next, an operation of the semiconductor device 6 is described as follows. A predetermined positive voltage is applied to the drain electrode 20, and both of the N+ type source region 32 and the P type body region 30 are grounded. Then, another predetermined positive voltage is applied to the trench gate electrode 36, so that the current flows from the N+ type drain region 22 to the N+ type source region 32. Specifically, when the positive voltage is applied to the trench gate electrode 36, electrons in the P type body region 30 are concentrated to a portion facing the trench gate electrode 36 so that an N type channel is formed. Electrons in the P− type region 24a is concentrated to a portion facing the bottom of the trench gate electrode 36 so that another N type channel region is formed. Thus, the electrons supplied from the N+ type source region 32 flow through the P type body region 30 and the P− type region 24a. Specifically, the electrons flow through the N type channel of the P type body region 30, which is disposed on the P type column 24 and faces the side of the trench gate electrode 36, and the portion of the P− type region 24a facing the bottom of the trench gate electrode 36. Then, the electrons flow through the N type column 26, and reach the N+ type drain region 22.
Preferably, the P− type region 24a is formed in a portion including the N type channel of the p type column 24. In this case, the N type channel is easily formed when the positive voltage is applied to the trench gate electrode 36.
One of the characteristics in the semiconductor device 6 is such that the P− type region 24a is formed on the P type column 24. Therefore, the impurity concentration of a portion of the P type column 24 adjacent to the trench gate electrode 36 can be set to be lower than that of the P type body region 30. Specifically, the impurity concentration of the P− type region 24a is lower than that of the P type body region 30. Therefore, the impurity concentration of the P type column 24 except for the P− type region 24a can be set to be comparatively higher independently from the impurity concentration of the P type body region 30. Thus, the column width of the P type column 24 can be narrowed. Therefore, it is not necessary to narrow the column width of the N type column 26, so that the cross sectional area of the N type column 26 does not become smaller. Specifically, a proportion of the cross sectional area of the N type column 26 in the whole area of the drift region 23 does not reduced substantially. Therefore, the column width of the N type column 26 can be widened, and the impurity concentration of the N type column 26 can become higher. Thus, the on state resistance of the N type column 26 is much reduced.
Further, in the semiconductor device 6, a floating potential state is prevented from occurring, so that the characteristic of the withstand voltage is stabilized.
Further, the process for forming the P type column 24 and the process for forming the P type body region 30 can be performed successively.
Furthermore, since the P− type region 24a is formed, the channel resistance is reduced. Further, the on state resistance of the N type column 26 is also reduced.
Next, two different methods for manufacturing the semiconductor device 6 are described as follows with reference to the drawings of
[First Method]
The first method for manufacturing the semiconductor device 6 is shown in
Then, as shown in
Next, as shown in
As shown in
Next, as shown in
[Second Method]
The second method for manufacturing the semiconductor device 6 is shown in
Thus, the doped P− type semiconductor thin film 70 becomes a part of the N type column 26. Further, the un-doped P− type semiconductor thin film 70, which is disposed under the mask 60 and is not implanted with the N type impurity, becomes the P type region 24a. Next, the mask 60 is etched and removed. Then, a P type crystal film is deposited by the epitaxial method such as the CVD method or the like so that the P type body region 30 is formed. After that, the trench gate electrode 36 is formed by the same manner as the first method. Thus, the semiconductor device 6 is completed.
A semiconductor device 7 according to a fourth embodiment of the present invention is shown in
In the semiconductor device 7, the proportion of the cross sectional area of the N type column 26 in the whole area of the drift region 23 does not reduced substantially. Therefore, the column width of the N type column 26 can be widened, and the impurity concentration of the N type column 26 can become higher. Thus, the on state resistance of the N type column 26 is much reduced.
Further, the process for forming the P type column 24 and the process for forming the P type body region 30 can be performed successively.
Next, a method for manufacturing the semiconductor device 7 is described as follows with reference to the drawings of
Next, as shown in
Next, the sidewall of the trench is oxidized so that an oxide film 50 is formed. The thickness of the oxide film 50 is thicker than that of the gate insulation film 34, which is formed later. The oxide film 50 can be formed by a conventional sacrifice oxidation method. When the sidewall of the trench is oxidized, the impurity of the P type column 24 is segregated to the oxide film 50 during the oxidation process. Specifically, the impurity of the P type column 24 disposed near the interface between the oxide film 50 and the P type column 24 is segregated (i.e., the impurity is distributed again). Thus, the impurity concentration of the parts of the P type body region 30 and the P type column 24 facing the trench is reduced so that the P− type region 24a is formed.
As shown in
In the above method, the process for forming the oxide film 50 can be omitted so that the trench gate electrode 36 is formed directly. In this case, the semiconductor device 7 has the impurity concentration of the P type column 24 equal to that of the P type body region 30.
Such changes and modifications are to be understood as being within the scope of the present invention as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2003-179635 | Jun 2003 | JP | national |
This application is a division of application Ser. No. 10/872,789 filed on Jun. 22, 2004, which is based on Japanese Patent Application No. 2003-179635 filed on Jun. 24, 2003, the disclosure of which is incorporated herein by reference.
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| Number | Date | Country |
|---|---|---|
| A-2000-260984 | Sep 2000 | JP |
| A-2001-127289 | May 2001 | JP |
| A-2002-203963 | Jul 2002 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20060138407 A1 | Jun 2006 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10872789 | Jun 2004 | US |
| Child | 11356984 | US |
