This application claims the benefits of prior Chinese Patent Application No. 201210258807.6 filed on Jul. 24, 2012, titled “method for manufacturing a semiconductor device”, which is incorporated herein by reference in its entirety.
The present invention relates to the field of manufacturing semiconductor integrated circuits. In particular, the present invention relates to a method of manufacturing a MOSFET having an increased contact region.
As the feature size of MOSFET are scaled continuously, the proportion of parasitic resistance in the total resistance of the device is growing, which seriously restricts the enhancement of properties of small size devices. The existing structure/method to reduce parasitic resistance comprises forming raised source/drain, forming a metal silicide in/on the source/drain region, increasing contact area, and so on.
However, no matter which structure/method is used, there is still a large distance between the contact area (or contact aperture, CA) and the gate spacer, and the distance of carriers of electrons/holes traveling from the source region to the drain region through the channel region is still large. Thus, parasitic resistance still cannot be effectively reduced and the enhancement of the device performance is limited.
In view of the above, one aspect of the present invention is to provide a new manufacturing method of a contact sacrificial layer process to substitute for the traditional replacement gate process, and to reduce the distance between the contact region and the gate significantly, thereby effectively reducing the parasitic resistance of the device.
The above aspect of the present invention is achieved by providing a method for manufacturing a semiconductor, comprising: forming a contact sacrificial layer on a substrate, etching the contact sacrificial layer to form a contact sacrificial pattern, wherein the contact sacrificial layer covers source and drain regions and has a gate trench that exposes the substrate; forming a gate spacer and a gate stack structure in the gate trench; partially or completely etching off the contact sacrificial pattern that covers the source region and the drain region so as to form a source/drain contact trench; and forming a source/drain contact in the source/drain contact trench.
The contact sacrificial layer includes a first contact sacrificial layer and a second contact sacrificial layer.
The first contact sacrificial layer includes strained Si, SiGe, Si:C, polycrystalline silicon, amorphous silicon, microcrystalline silicon, amorphous carbon, silicon oxide, silicon nitride, or any combination thereof; and the second contact sacrificial layer includes single crystal silicon, polycrystalline silicon, amorphous silicon, microcrystalline silicon, amorphous carbon, silicon oxide, silicon nitride, or any combination thereof
The step of forming a source/drain contact trench comprises: partially etching off the sacrificial; or completely etching off the second contact sacrificial layer and partially etching off the first contact sacrificial layer; or completely etching off the second contact sacrificial layer and the first contact sacrificial layer; or completely etching off the second contact sacrificial layer and the first contact sacrificial layer and partially etching the substrate.
A contact sacrificial layer is formed by epitaxial growth and is doped to have a first conductivity type.
After a contact sacrificial layer is formed, the contact sacrificial layer and the substrate are etched to form a shallow trench, and the shallow trench is filled with an insulating material to form a shallow trench isolation.
After a gate trench is formed, the shallow trench isolation is etched such that it is tilted towards the isolation region in the width direction of the active region.
After a contact sacrificial pattern is formed, a lightly-doped source/drain region is provided in the substrate on both sides of the gate trench.
The formation of a gate stack structure comprises depositing a gate insulating layer of a high-k material, a work function adjustment layer of a metal nitride, and a resistance adjustment layer of a metal in the gate trench.
The step of forming a source/drain contact further comprises: forming a metal silicide in the source/drain contact trench; depositing a liner and a filling layer sequentially on the metal silicide; and planarizing the filling layer and the liner until the gate stack structure is exposed.
By means of a double-layer contact sacrificial layer process, the method for manufacturing a semiconductor device according to the present invention effectively reduces the spacing between the gate spacer and the contact region and increases the area of contact region, thus effectively reducing the parasitic resistance of the device.
The technical solutions of the present invention are described in detail with reference to the drawings, wherein:
The characteristics and technical effects of the technical solution of the present invention is described in detail referring to the figures in combination with schematic embodiments. What should be noted is that: similar reference signs denote similar structures, and the terms “first”, “second”, “above”, “below”, “thick”, “thin”, and so on used in the present application can be used for modifying various device structures. These modifications, unless otherwise stated, do not imply the space, order, or hierarchical relationship of the device structure modified.
Referring to
As shown in
By using a conventional method such as LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, and sputtering and properly controlling the process parameters, a first contact sacrificial layer 2 is epitaxially grown on the substrate 1. The first contact sacrificial layer 2 is used for the actual source/drain region (as a portion of the raised source/drain) of the device to be formed, the material of which may be strained Si, SiGe, Si:C, or any combination thereof, and the thickness of which may be, for example, 10 to 100 nm. Since the lattice constant of the material of the first contact sacrificial layer 2 and that of the material of the substrate 1 are different, stress can be applied to the channel region, thereby improving the carrier mobility and enhancing the driving capability of the device. Preferably, by epitaxial growth and simultaneously in-situ doping or an additional ion implantation process after epitaxial growth, the first contact sacrificial layer 2 has a first conductivity type, e.g., n or p type. Furthermore, the first contact sacrificial layer 2 can also be polycrystalline silicon, amorphous silicon, microcrystalline silicon, amorphous carbon, silicon oxide, or silicon nitride, etc. At this time, the first contact sacrificial layer 2 will be completely removed in the subsequent process of forming a source/drain contact trench as shown in
Subsequently, by a similar epitaxial process, a second contact sacrificial layer 3 is further epitaxially formed on the first sacrificial layer 2 for defining the region for forming a source/drain contact later, which plays a similar function to the dummy-gate in the gate-last process and therefore is also referred to as a dummy source/drain contact region. The material of the second contact sacrificial layer 3 can be the same as the substrate 1, e.g., Si (which may be single crystal silicon, or polycrystalline silicon, amorphous silicon, microcrystalline silicon; in this case, the second contact sacrificial layer 3 is not completely removed by etching in the subsequent process but part of it is retained to be used as a portion of the raised source/drain region). Alternatively, the material of the second contact sacrificial layer 3 can be different from that of the substrate 1, which may be, for example, amorphous carbon, silicon nitride, silicon oxide, or silicon nitride oxide (in this case, the second contact sacrificial layer 3 will be completely removed by etching in the subsequent process until the first contact sacrificial layer 2 is exposed). The second contact sacrificial layer 3 has a thickness greater than that of the first contact sacrificial layer 2, preferably 40 to 500 nm. The sum of the thickness of the first contact sacrificial layer 2 and the second sacrificial layer 3 is greater than the height of the gate to be formed later, for example, 50 to 500 nm. Preferably, when the material of the second contact sacrificial layer 3 includes Si (i.e., when a part would be retained to be used as a portion of the raised source/drain region), by epitaxial growth and simultaneously in-situ doping or an additional ion implantation process after epitaxial growth, the second contact sacrificial layer 3 also has a first conductivity type with higher concentration, e.g., n+ or p+.
As shown in
As shown in
Preferably, a source/drain lightly doped process is performed to form a source/drain lightly doped region in the substrate. For example, with a photoresist pattern 5 and the contact sacrificial layer 3/2 below as a mask, angled source/drain ion implantation with a low dose and low energy may be performed, and the implantation position of the dopants may be controled by Shadow Effect so as to form a lightly-doped source/drain extension region 1A, and a Halo source/drain doping region 1B in the substrate below the source/drain extension region. Subsequently, rapid annealing (for example, laser rapid annealing) is performed to activate the dopants. The type, dose and concentration of the implanted ions may be determined in accordance with the requirements of the electrical properties of the device. In addition, optionally, a spacer with a diffusion source may be provided on both sides of the contact sacrificial layer 3/2 in the gate trench 6 to form a lightly-doped source/drain extension region IA by ion diffusion effect, and then the spacer may be removed.
Referring to
Referring to
Referring to
In particular, if the second contact sacrificial layer 3 and the first contact sacrificial layer 2 (or no in-situ doping is performed during the process of epitaxially growing contact sacrificial layers 2/3 and no additional ion injection is performed after epitaxial growth) are completely removed, the substrate exposed in the source/drain contact trench 3A (or the second contact sacrificial layer 3 and/or the first contact sacrificial layer 2) is heavily doped to form a heavily doped region of n+ or p-type as the source/drain heavily doped region.
Thereafter, a metal thin layer (not shown), e.g., Ni, Pt, Co or Ti, or combinations thereof, is formed by sputtering and evaporation in the source/drain contact trench 3A, and then rapid annealing or low temperature annealing (400 to 600° C.) is performed, so that the metal thin layer reacts with Si in the source/drain region to form a metal silicide 10 for further reducing contact resistance. The unreacted metal thin layer is stripped off. In this case, since STI 4 of an oxide material and the gate spacer 7 of a silicon nitride material 7 do not react with the metal thin layer, the metal silicide 10 is only formed in the source/drain region.
Referring to
Referring to
By means of a double layer contact sacrificial layer process, the method for manufacturing a semiconductor device according to the present invention effectively reduces the spacing between the gate spacer and the contact region and increases the contact area, thus effectively reducing the parasitic resistance of the device.
Although the present invention is described with reference to one or more exemplary embodiments, those skilled in the art know that a variety of suitable changes and equivalents can be made to the method of forming a device structure without departing from the scope of the present invention. Furthermore, from the teachings disclosed herein, many amendments suitable for specific situations or materials can be made without departing from the scope of the invention. Accordingly, the aspect of the present invention is not limited to particular embodiments used for achieving the best modes to carry out the present invention, while the device structure and its manufacturing method disclosed will include all embodiments that fall within the scope of the invention.
Number | Date | Country | Kind |
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201210258807.6 | Jul 2012 | CN | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/CN2012/079694 | 8/3/2012 | WO | 00 | 1/23/2015 |