The present application claims priority to Chinese Patent Application No. 202011263819.9 filed with the China National Intellectual Property Administration (CNIPA) on Nov. 12, 2020, the disclosure of which is incorporated herein by reference in its entirety.
Embodiments of the present application relate to the technical field of semiconductor power devices, for example, a method for manufacturing a semiconductor power device.
In the related art, a method for manufacturing a semiconductor power device includes the following steps: first, as shown in
The present application provides a method for manufacturing a semiconductor power device to reduce the gate-source capacitance of the semiconductor power device and reduce the gate-source leakage of the semiconductor power device.
The present application provides a method for manufacturing a semiconductor power device. The method includes the steps below.
A first recess is formed in an n-type substrate and a field oxide layer and a shielded gate are formed in the first recess.
The field oxide layer is etched in a self-aligned manner by taking the n-type substrate and the shielded gate as self-aligned boundaries, to etch away the field oxide layer in the upper portion of the first recess and to form a second recess in the upper portion of the first recess and between the shielded gate and the n-type substrate.
A first insulating dielectric layer is formed. The first insulating dielectric layer covers sidewalls of the second recess and the bottom of the second recess.
A layer of photoresist is formed. The photoresist fills the second recess.
Photolithography is performed, to expose the first insulating dielectric layer located in the second recess and on sides close to the n-type substrate; then the first insulating dielectric layer located in the second recess and on sides close to the n-type substrate is etched away; and the first insulating dielectric layer located in the second recess and on sides close to the shielded gate is retained.
The photoresist is removed and a gate dielectric layer and a gate are formed in the second recess.
Optionally, the method for manufacturing a semiconductor power device according to the present application further includes the steps below.
A p-type body region is formed in the n-type substrate.
An n-type source region is formed in the p-type body region.
Optionally, in the method for manufacturing a semiconductor power device according to the present application, the first insulating dielectric layer is a silicon oxide layer.
Optionally, in the method for manufacturing a semiconductor power device according to the present application, the step in which the first insulating dielectric layer is formed includes the step below.
The process of sub-atmospheric chemical vapor deposition is used to form the first insulating dielectric layer.
Optionally, in the method for manufacturing a semiconductor power device according to the present application, the step in which the first insulating dielectric layer located in the second recess and on sides close to the n-type substrate is etched away includes the step below.
The process of wet etching is used to etch away the first insulating dielectric layer located in the second recess and on sides close to the n-type substrate.
Optionally, in the method for manufacturing a semiconductor power device according to the present application, the n-type substrate is a silicon substrate.
Optionally, in the method for manufacturing a semiconductor power device according to the present application, the thickness of the first insulating dielectric layer is greater than the thickness of the gate dielectric layer.
In the method for manufacturing a semiconductor power device according to the present application, the photoresist is formed on the first photoresist and serves as a mask to retain the first insulating dielectric layer located in the second recess and on sides close to the shielded gate. With this arrangement, the thickness of the first insulating dielectric layer is relatively great. When the gate is insulated from the shielded gate by the first insulating dielectric layer, the gate-source capacitance is reduced, the gate-source leakage is reduced, and the reliability of the semiconductor power device is enhanced.
Technical solutions of the present application are described completely hereinafter in conjunction with the drawings in embodiments of the present application. Apparently, the described embodiments are part, not all, of embodiments of the present disclosure. Meanwhile, to illustrate the embodiments of the present application clearly, in the schematic views illustrated in drawings of the description, thicknesses of layers and regions described in the present application are enlarged, and dimensions illustrated in the views do not represent the actual dimensions.
First, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Finally, according to a traditional process, a gate dielectric layer and a gate are formed in the second recess. Moreover, a p-type body region is formed in the n-type substrate; an n-type source region is formed in the p-type body region; and then the semiconductor power device can be obtained after layers, for example, an insulating dielectric layer and a metal layer, are formed.
In the method for manufacturing a semiconductor power device according to the present application, the first insulating dielectric layer and the gate dielectric layer are formed through processes in two steps so that the thickness of the first insulating dielectric layer is greater than the thickness of the gate dielectric layer. Moreover, since the gate is insulated from the shielded gate by the first insulating dielectric layer, the arrangement of increasing the thickness of the first insulating dielectric layer helps reduce the gate-source capacitance, reduce the gate-source leakage, and enhance the reliability of the semiconductor power device.
Number | Date | Country | Kind |
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202011263819.9 | Nov 2020 | CN | national |
Filing Document | Filing Date | Country | Kind |
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PCT/CN2020/131291 | 11/25/2020 | WO |