Patent Application
20070169688
1. Technical Field
A silicon wafer and a method for manufacturing the same are disclosed. The disclosed wafer has a high density and uniform bulk micro defect (BMD) concentration in a bulk area of the wafer disposed between front and rear denuded zones (DZ).
2. Discussion of the Related Art
As semiconductor devices become ultra-minute with sizes under 0.1 μm and more highly integrated, the silicon wafers from which these devices are made have become larger, in excess of 300 mm. While the development of large wafers provides numerous advantages, defects in the large wafers must be avoided.
Specifically, manufacturers are required to provide a “non-defect” layer in an active region of the wafer or the resulting semiconductor device. Manufacturers have also been required by customers to effectively remove impurities such as metal particles that can be generated during the manufacturing process. Further, manufacturers have been required to increase the bulk micro defect “BMD” density which consists primarily of oxygen precipitates and the bulk or oxidation stacking fault in the bulk area beneath the active region of the resulting device.
In achieving these goals, numerous defects must be eliminated, manipulated or controlled. Of the numerous defects that may be created, crystal originated pits (COP), flow pattern defect (FPD), laser scattering tomography defect (LSTD) and a slip occurrence are of primary interest.
COP appears on the surface layer of a wafer is of a size in the range of 0.09˜0.12 μm and can be observed with a SP1-TBI scanner and by re-processing with a standard cleaning (SC1) solution. COP appears as a pit on the wafer. COP is a crystal defect induced during the crystal growing process. FPD is related to the oxide film, is a defect with a ripple shape, and is detected being etched selectively by using an etching solution of group of potassium bichromic-acid, hydrofluoric acid (HF). FPD may be confirmed with a microscope. LSTD, a defect detected by a laser scattering tomography, has been known as a micro defect generated during a crystal growing process. “Slip” occurs when significant temperature gradients are present within the wafer during heat treatments and from differences in coefficients of heat expansion of the silicon wafer and the silicon carbide boat used during heat processing of the wafer. COP is the most influential defect component and FPD density and LSTD may be used to confirm COP directly or indirectly.
If a customer proposes a COP free zone up to a 10 μm depth from the surface of the water, a SP1-TBI or a method of etching process may be used to detect defects on the surface of the wafer, and LSTD can be monitored up to a 5 μm depth. As a result, a wafer manufacturer confirms COP defects, or the lack thereof, indirectly with a combination of the SP1-TBI and LSTD with additional polishing up to a 10 μm depth.
There are many oxygen impurities found in silicon wafers produced by processing single-crystalline silicon, pulled and grown by a Czochralski CZ method. The oxygen impurities become oxygen precipitates which generates dislocations or defects. When the oxygen precipitates are on the surface of the wafer, they increase leakage current and degrade an oxide film inside-pressure, which are both disadvantageous characteristics for a semiconductor device.
Furthermore, silicon wafers must include a denuded zone (DZ) from a surface or edge of the wafer to a predetermined depth, in which there is no dislocation, stacking defect or oxygen precipitates. DZs are typically required at the front and the rear of the wafer. To achieve these objectives, several methods for manufacturing silicon wafers are provided.
First, it has been attempted to make a non-defect zone in an active region of device by manufacturing a pure single-crystalline silicon without defects when producing a silicon ingot for fabricating the silicon wafer. However, in this case, the oxygen precipitates are reduced in a bulk zone, and therefore the BMD density is also low. Also manufacturing pure single-crystalline silicon is costly.
Second, to provide a non-defect zone in the active region of the semiconductor device, a method exists for making an epitaxial-type wafer grown for an epitaxial layer by using a chemical vapor deposition (CVD) method on the silicon wafer. While, this method has improved techniques over the pure single-crystalline silicon manufacturing method discussed above and the annealed wafer manufacturing method discussed below, it is very costly.
Third, an annealing method is used for making non-defect zones in the active region of semiconductor devices. In this method, by removing the crystal originated pit generated during crystal growth by way of a heat treatment process, the COP is eliminated from the active region of semiconductor device. Also, DZ zones without oxygen precipitates can be provided up to a predetermined depth by way of an oxygen out-diffusion in the surface area. Moreover, annealing can effectively eliminate impurities such as a metal by increasing BMD density, the oxygen precipitates in the bulk zone.
However, current annealing techniques require numerous adjustments to the gas atmosphere, temperature ramp-up/down rates and heat treatment temperatures/times, all of which make control of the process very difficult, costly and unreliable. Consequently, current annealing processes generate defects such as slip during the high temperature processes, or the annealed wafer can't be manufactured with a uniform and sufficient non-defect zone and high BMD density. Therefore, an improved annealing type process is urgently needed.
A silicon wafer is disclosed that has a uniform and sufficient front and rear denuded zones (DZs) and a COP free zone in an active region of the wafer. The disclosed wafer also has a high density of BMDs in the bulk zone of the wafer disposed between the front end rear DZs.
A method for manufacturing a silicon wafer on the order of 300 mm that controls a slip due to a high temperature process used to remove defects in the wafer, provides a uniform and a sufficient DZ and a COP free zone in an active region of wafer, and provides a high density of BMDs in the bulk zone.
One disclosed silicon wafer comprises: a first denuded zone (DZ) formed over a predetermined depth from a surface of a front side of the wafer, without a crystal originated pit (COP) defect; a second denuded zone (DZ) formed over a predetermined depth from a surface of a rear side of the wafer, without a crystal originated pit (COP) defect; and a bulk zone formed between the first and second denuded zones, in which a concentration profile of bulk micro defects (BMD) is uniform from the front side towards the rear side of the wafer; and wherein the silicon wafer is doped with nitrogen in a concentration ranging from about 1×1012 atoms/cm3 to about 1×1014 atoms/cm3.
Preferably, the concentration of the BMDs is in the range of from about 1.0×108 to about 1.0×1010 ea/cm3 or defects/cm3 in the bulk zone between the first and second denuded zones.
Preferably, depths or widths of the first and second denuded zone are within the range of from about 5 μm to about 40 μm respectively from the front and the rear sides of the wafer.
Furthermore, a method of manufacturing a silicon wafer is disclosed that comprises: (a) preparing a silicon wafer having a front side, a rear side, and a zone disposed between the front and rear sides; (b) loading the silicon wafer on a heat treatment apparatus heated to a first temperature; (c) pre-heating the silicon wafer to the first temperature for a predetermined time; (d) raising the temperature of the heat treatment apparatus to a second higher temperature at a first temperature ramp-up rate; (e) raising the temperature of the heat treatment apparatus up to a third still higher temperature higher at a second temperature ramp-up rate; (f) raising the temperature of the heat treatment apparatus up to a fourth still higher temperature higher at a third temperature ramp-up rate; (g) heating the silicon wafer at the fourth temperature by maintaining the fourth temperature for a predetermined time; and (h) reducing the temperature of the heat treatment apparatus towards the first temperature; wherein the second temperature ramp-up rate is smaller than the first temperature ramp-up rate; parts (c), and (f) through (h) are carried out in atmosphere of inert gas; and parts (d) and (e) are carried out in atmosphere of hydrogen.
Preferably, the preparing of the silicon wafer includes the steps of: dipping a seed crystal in a silicon melt and growing a single-crystalline silicon by pulling up the seed crystal while adjusting a crystal growing speed and a temperature gradient along a growing axis at a boundary of solid and liquid phase boundary; slicing the grown single-crystalline silicon into shapes of wafers; and removing slicing damage generated from slicing and rounding sides of the sliced wafer or etching a surface of the sliced wafer; wherein the single-crystalline silicon is grown with nitrogen doped in concentration ranging from about 1×1012 atoms/cm3 to about 1×1014 atoms/cm3 so as to increase precipitated oxygen.
After part (h), the disclosed method preferably further comprises one or more of: polishing the surface of the silicon wafer; making the surface of the silicon wafer specular; and cleaning the silicon wafer.
Preferably, the first temperature is about 500° C., the second temperature is about 950° C., the third temperature is about 1100° C. and the fourth temperature is about 1200° C.
Preferably, the first temperature ramp-up rate is about 10° C./min, and the second temperature ramp-up rate is about 5° C./min.
Preferably, the third temperature ramp-up rate is from about 0.1 to about 5° C./min.
Part (g) is preferred to perform for a time period ranging from about 1 to about 120 minutes at the fourth temperature.
Preferably, part (h) includes: reducing the temperature down to about the third temperature at a first temperature ramp-down rate; reducing the temperature down to about the second temperature at a second temperature ramp-down rate; and reducing the temperature down to about the first temperature at a third temperature ramp-down rate.
Preferably, the third temperature ramp-down rate is larger than the second temperature ramp-down rate.
Preferably, the first temperature ramp-down rate is from about 0.1 to about 5° C./min.
Preferably, the second temperature ramp-down rate is about 5° C./min and the third temperature ramp-down rate is about 10° C./min.
a and 3b are bar graphs illustrating the relationship between the number of localized light scattering (LLS) and LLS size according to whether or not nitrogen is present.
a and 7b graphically illustrates variations in zone depth without COPs by varying heat treatment time of a nitrogen-doped wafer as measured by LLS.
a and 8b graphically illustrate the relationship between denuded zone depth and bulk micro defect density according to a temperature ramp-up rate.
a and 11b graphically illustrates the relationship between overall slip length and a temperature ramp-up rate.
a and 15b graphically illustrates the relationship between resistivity, depth from the wafer surface, according to the gas atmosphere.
Disclosed methods for manufacturing silicon wafers will now be described in detail with reference to the accompanying drawings.
Referring to
Next, the ingot is sliced into shapes of wafer (S20).
Slicing damages occurred in performing the slicing process are removed, and an etching process is carried out for etching a surface or rounding a side of the sliced wafer (S30).
A donor killing process is the performed (S30), in which oxygen is generated from a crystal growing step included in a silicon wafer which includes oxygen precipitates from a heat treatment process. That is, approximately 1016 atoms/cm3 of oxygen atoms among the approximately 1018 atoms/cm3 of oxygen atoms included in crystal growing step of the silicon wafer donate an electron by way of collecting a plurality of oxygen atoms during a single-crystal peak cooling process and then they become like donors. It is difficult to get a target resistance ratio due to those electron donors even though adding a dopant for balancing the resistance ratio of wafer. Therefore, the donor killing process is carried out to make the oxygen generated from the crystal growing step into the oxygen precipitates to prevent the oxygen from acting as a donor (S40). The donor killing process includes a heat treatment.
Next, the surface of the silicon wafer (S50) is polished, and the surface of the silicon wafer is made specular (S60) and the silicon wafer is cleaned (S70). The silicon wafer is then packaged.
Part (S10) for growing the single-crystalline silicon will be briefly described. First, a necking step is carried out to grow a thin and long crystal from the seed crystal, and shouldering step is followed to make the single-crystalline silicon a target diameter by growing it in an outward direction to increase the diameter of the crystal. A crystal with a constant diameter is grown after completing the shouldering step, which is referred to as a body growing step. The body growing step is performed over a predetermined length, as the diameter of the crystal is being increased. The crystal growing step is completed by carrying out a tailing process step which separates the crystal from the silicon melt. The crystal growing process is carried out at a hot zone. A grow is disposed between the silicon melt and the ingot contact at the time that the silicon melt is growing to the single-crystal ingot. The grower includes a crucible, a heater, a thermostat structure, an ingot pulling apparatus, a pedestal and so on.
The silicon wafer is fabricated by performing processes such as cutting off, polishing, and cleaning up the nitrogen-doped silicon ingot under a predetermined concentration.
Referring to
The gas atmosphere in the heat treatment apparatus is changed to a hydrogen gas atmosphere, the temperature in the heat treatment apparatus is increased to a second temperature (for example, about 950° C.) at about first temperature ramp-up rate (for example, about 10° C./min).
When the temperature in the heat treatment apparatus has risen to the target second temperature, the temperature in the heat treatment apparatus is increased to a third temperature (for example, about 1100° C.) using a second temperature ramp-up rate (for example, about 5° C./min). The second temperature ramp-up rate is preferably smaller than the first temperature ramp-up rate to avoid slip occurrence. When increasing the temperature, the second ramp-up temperature rate must be decreased or reduced to slow the heating. Thus, the second temperature ramp-up rate must be smaller than that of the first temperature ramp-up rate to control slip due to any temperature variation between the wafer center and its edge.
When the temperature in the heat treatment apparatus is heated up to the target third temperature, the gas atmosphere in the heat treatment apparatus is changed to the inert gas atmosphere, for instance, an argon gas atmosphere, and the temperature in the heat treatment apparatus is risen to the fourth temperature (for example, about 1200° C.) at a third temperature ramp-up rate (for example, in the range of from about 0.1 to about 5° C./min)
When the temperature in the heat treatment apparatus is heated up to the target fourth temperature, the apparatus carries out the heat treatment at a high temperature by maintaining the fourth temperature for a time period ranging from about 1 to about 120 minutes. It is preferable to maintain the apparatus at the fourth temperature for about 60 minutes for assuring a suitable level of denuded zone depth and BMD density. If the fourth temperature is maintained for over 120 minutes, a zone without COP is deeper, but the diffusion furnace can't be used for a long time and productivity is decreased.
The temperature is then reduced down to a fifth temperature with the first temperature ramp-down rate (for example, in the range of from about 0.1 to about 5° C./min). The fifth temperature is preferably about the same as the third temperature.
After the temperature has been reduced to the fifth temperature, it is reduced again to a sixth temperature at the second temperature ramp-down rate (for example, about 5° C./min). The sixth temperature is preferably about the same as the second temperature.
After the temperature has been reduced to the sixth temperature, it is reduced further to a seventh temperature at a the third temperature ramp-down rate (for example, about 10° C./min). The seventh temperature is preferably about the same as the first temperature. The third temperature ramp-down rate is preferable larger than that of the second temperature.
The heat treatment process of
a and 3b are diagrams illustrating the number of localized light scattering (LLS) by size regardless of whether nitrogen doping has been carved out.
Therefore, during manufacturing a silicon ingot, it is not advantageous to cause a crystal defect by nitrogen by way of increasing the nitrogen concentration over 1×1014 atoms/cm3. It is preferred to control the nitrogen concentration below 1×1014 atoms/cm3 when adding the nitrogen to the single-crystalline silicon for manufacturing an annealed wafer.
The conditions of the heat treatment include the: changing an atmosphere in a diffusion furnace to an argon gas atmosphere, putting a silicon wafer into the diffusion furnace, and pre-heating and maintaining the silicon wafer at the temperature of 500° C.; heating up the temperature up to 950° C. at a heating rate of about 10° C./min after changing the gas atmosphere in the diffusion furnace to a hydrogen H2 atmosphere; heating up the temperature up to 1100° C. at a heating rate of 5° C./min; heating up the temperature up to about 1200° C. at a heating rate of about 1° C./min after hanging the gas atmosphere in the diffusion furnace to an argon atmosphere; maintaining it at the temperature of about 1200° C. for about 60 minutes; reducing the temperature to about 1100° C. at a cooling rate of about 1° C./min; reducing the temperature to about 950° C. at a cooling rate of about 5° C./min; and reducing the temperature to about 500° C. at a cooling rate of about 10° C./min. The GOI estimation is performed after setting the thickness of the oxide film at 120 Å, the thickness of the polysilicon at 1000 Å, and a transistor area at 0.2 cm2 and then using an HP4156A, as a breakdown voltage measuring equipment. As shown in the part (a) in
a and 7b are diagrams illustrating results monitoring variation of a zone depth without COP according to a nitrogen-doped wafer by way of variation of LLS. The parts (a), (b), (c), (d), and (e) in
Here, the temperature of the heat treatment is fixed at about 1200° C. The heat treatment is performed by the same condition as the case illustrated with reference to
Furthermore, as described in
a is a diagram illustrating a denuded zone depth (corresponding to the part (a) in
b is a diagram illustrating the denuded zone depth (corresponding to the part (b) in
a and 11b are diagrams illustrating the overall slip length according to the temperature ramp-up time.
a and 11b show results of performing the heat treatment process by fixing the heat treatment temperature at 1200° C., the heat treatment time for 60 minutes, and the oxygen concentration in 12.5 ppma. The other heat treatment conditions are same to the conditions illustrated with reference to
In general, when an external stress is occurred at the single-crystalline silicon grid, and this stress is pressed more than silicon yield stress, a variation thereby is defined as a strain or a dislocation. If the external stress is continually pressed, the dislocation moves among the grids, which is called as a slip. The slip does not come to easily generated in case that the movement of dislocation interfere with precipitates in the silicon wafer, in case that the density of precipitates increase and thus the intervals among the precipitates are narrow. The slip generation can be decreased by increasing the precipitate density in the wafer due to a dislocation pinning effect. It will be described the process that oxygen precipitates interrupt dislocation movement in the silicon wafer in
On the other hand, as illustrated in
Therefore, it is advantageous that the oxygen concentration is as low as possible for assuring a sufficient DZ depth and a zone depth without COP, and the problem of slip generation thereby can be solved by properly adjusting the heat treatment conditions. According to the testing results in the embodiment, the slip happens below 1 mm when the first and second temperature ramp-up rates is set at 5° C./min at the same time at a low oxygen concentration of 11 ppma.
It is impossible to control a damage shown by a point below 1 mm in general due to contact between the wafer and a boat during the heat treatment for manufacturing an annealed wafer. Therefore, it should be confirmed whether the slip transits from the damage-occurred area to a semiconductor device driving zone after two steps of device heat treatments (4 hours at 800° C. and 16 hours at 1000° C.). As shown in
a and 15b are diagrams illustrating variations of resistivity according to a gas atmosphere.
As such, when the gas atmosphere is changed from the inert gas atmosphere to the hydrogen atmosphere, it is important for the temperature period of the heat treatment at the hydrogen atmosphere. The hydrogen should be added as small as completely eliminating the native oxide layer, but if adding more than that, it eliminates the native oxide film on the surface after that, the boron atom inside wafer reversely diffuse into the outside of wafer. As a result of this, the resistivity on the surface is rather increased. Furthermore, in case of performing the heat treatment at over 1100° C. for a long period of time, it causes increasing of metal contamination of the wafer. In general, in case of performing the heat treatment only at the Ar atmosphere, it has increased the life time of main consumable such as quartz more than in case of performing the heat treatment at the hydrogen atmosphere, and has been known as being advantageous in the side of wafer contamination. Accordingly, as described above, it is preferable to designate and control the heat treatment period properly at the hydrogen atmosphere.
According to the monitoring result, when the heat treatment is performed under a hydrogen atmosphere during the period between the first temperature of 500° C. and the third temperature of 1100° C., and performed under the argon atmosphere at the rest temperature period, it is possible to get a very uniform resistivity profile by eliminating only the native oxide layer including the boron atom on the wafer surface, as illustrated in
The disclosed methods can control the slip generation by a high-temperature process, which has been a problem of an annealed wafer. Furthermore, it is possible to provide a uniform and sufficient DZ zone and a zone without COP in an active region of device. Moreover, it is possible to manufacture a wafer with a uniform BMD and a high BMD density in the bulk zone between the denuded zones. Therefore, it is possible to increase the effect of gettering metal impurities such as Fe by forming a uniform and high density BMD under an active region of device.
Although the disclosed methods have been described in connection with certain embodiments and illustrated in the accompanying drawings, this disclosure is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of this disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2004-32633 | May 2004 | KR | national |
This is a division of copending, commonly assigned application Ser. No. 10/973,545 filed Oct. 26, 2004, the disclosure of which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10973545 | Oct 2004 | US |
| Child | 11651695 | Jan 2007 | US |
