Patent Application
20230069980
The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2021-146038, filed Sep. 8, 2021, the entire contents of which are incorporated herein by reference.
The present invention relates to a method for manufacturing a wiring substrate.
Japanese Patent Application Laid-Open Publication No. 2001-85837 describes a method for manufacturing a multilayer printed wiring board. The entire contents of this publication are incorporated herein by reference.
According to one aspect of the present invention, a method for manufacturing a wiring substrate includes forming a resin insulating layer on a first conductor layer such that the resin insulating layer covers the first conductor layer, applying a roughening treatment on a surface of the resin insulating layer on the opposite side with respect to the first conductor layer, forming an opening in the resin insulating layer after the roughening treatment on the surface of the resin insulating layer such that the opening penetrates through the resin insulating layer and exposes a portion of the first conductor layer, and forming a second conductor layer on the surface of the resin insulating layer such that the second conductor layer is formed in contact with the surface of the resin insulating layer and that a via conductor is formed in the opening of the resin insulating layer.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.
A wiring substrate manufactured using a method for manufacturing a wiring substrate according to an embodiment of the present invention is described with reference to the drawings. The drawings to be referenced below are drawn such that features of the embodiment are easily understood, without intending to show exact proportions of structural elements.
The wiring substrate 1 in the example illustrated in
A solder resist layer 110 is formed on the first build-up part 10. A solder resist layer 210 is formed on the second build-up part 20. Openings (110a) are formed in the solder resist layer 110, and conductor pads (12p) of the outermost conductor layer 12 in the first build-up part 10 are exposed in the openings (110a). Openings (210a) are formed in the solder resist layer 210, and conductor pads (22p) of the outermost conductor layer 22 in the second build-up part 20 are exposed in the openings (210a).
In the description of the method for manufacturing a wiring substrate of the embodiment and a wiring substrate to be manufactured, the conductor layer 121 of the first build-up part 10 in the wiring substrate 1 is also referred to as the first conductor layer 121. The insulating layer 111 that covers an upper side of the first conductor layer 121 is also referred to as the first resin insulating layer 111. The conductor layer 122 formed on an upper side of the first resin insulating layer 111 is also referred to as the second conductor layer 122.
In the description of the wiring substrate 1 and the method for manufacturing the wiring substrate 1, a side farther from the core insulating layer 101 is referred to as “upper,” “upper side,” “outer side,” or “outer,” and a side closer to the core insulating layer 101 is referred to as “lower,” “lower side,” “inner side,” or “inner.” Further, for the insulating layers and the conductor layers, a surface facing the opposite side with respect to the core substrate 100 is also referred to as an “upper surface,” and a surface facing the core substrate 100 side is also referred to as a “lower surface.” Therefore, in the description of the wiring substrate manufactured using the manufacturing method of the embodiment, a surface of the first conductor layer 121 facing the opposite side with respect to the core insulating layer 101 is also referred to as an upper surface of the first conductor layer 121.
A surface of the first resin insulating layer 111 facing the opposite side with respect to the core insulating layer 101, that is, a surface of the first resin insulating layer 111 on the opposite side with respect to the first conductor layer 121 is also referred to as an upper surface of the first resin insulating layer 111.
In the illustrated example, an outermost surface of the wiring substrate 1 formed of exposed surfaces of the conductor pads (12p) and the solder resist layer 110 is also referred to as a first surface (Fa). An outermost surface of the wiring substrate 1 that is on the opposite side with respect to the first surface (Fa) and is formed of exposed surfaces of the solder resist layer 210 and the conductor pads (22p) is also referred to as a second surface (Fb). That is, the wiring substrate 1 has the first surface (Fa) and the second surface (Fb) on the opposite side with respect to the first surface (Fa) as two surfaces that extend in a direction orthogonal to a thickness direction of the wiring substrate 1.
The conductor layers (102, 12, 121, 122, 22) of the wiring substrate 1 are patterned to have any conductor patterns. In the illustrated example, the outermost conductor layer 12 in the first build-up part 10 has conductor pads (12p) that are formed in patterns that are electrically and mechanically connected to connection terminals of a component that is mounted on the wiring substrate 1 when the wiring substrate 1 is used.
That is, the conductor pads (12p), which form the first surface (Fa), are used as connection parts when an external component is mounted on the wiring substrate 1, and the first surface (Fa) of the wiring substrate 1 is a component mounting surface on which multiple components are mounted. Electrodes of an external component are electrically and mechanically connected to the conductor posts (12p), for example, via a bonding material (not illustrated in the drawings) such as solder. As an external component, an electronic component such as a bare chip semiconductor is mounted on the component mounting surface.
The second surface (Fb), which is a surface on the opposite side with respect to the first surface (Fa), of the wiring substrate 1 in the example illustrated in
In the insulating layer 101 of the core substrate 100, through-hole conductors 103 are formed connecting the conductor layer 102 that forms the surface (F1) on the one side of the core substrate 100 and the conductor layer 102 that forms the surface (F2) on the other side of the core substrate 100. In the insulating layers (11, 111, 21), via conductors (13, 23) connecting the conductor layers sandwiching the insulating layers (11, 111, 21) are formed. In the illustrated example, each of the through-hole conductors 103 has a tapered shape that is reduced in diameter from both the surface (F1) on the one side and the surface (F2) on the other side toward a center portion in a thickness direction of the core substrate 100, and each of the via conductors (13, 23) has a tapered shape that is reduced in diameter from an outer side toward an inner side of the wiring substrate. It is also possible that each of the through-hole conductors 103 is formed to have substantially the same diameter in a length direction (the thickness direction of the core substrate 100), or to have a tapered shape that is reduced in diameter from one side toward the other side (for example, from the surface (F1) on the one side toward the surface (F2) on the other side).
Each of the insulating layers (101, 11, 111, 21) is formed, for example, using an insulating resin such as an epoxy resin, a bismaleimide triazine resin (BT resin) or a phenol resin. Each of the insulating layers may contain a reinforcing material (core material) such as a glass fiber and/or inorganic filler such as silica or alumina. Each of the solder resist layers (110, 210) may be formed using, for example, a photosensitive epoxy resin or polyimide resin, or the like.
Each of the conductor layers (102, 12, 121, 122, 22), the via conductors (13, 23), and the through-hole conductors 103 is formed using any metal such as copper or nickel, and, for example, formed of a metal foil such as a copper foil and/or a metal film formed by plating or sputtering or the like. Each of the conductor layers (102, 12, 121, 122, 22), the via conductors (13, 23), and the through-hole conductors 103 is illustrated in
On the surfaces of the conductor layers (102, 12, 121, 122, 22), an organic coating film (covering layer) is formed that improves adhesion between the conductor layers (102, 12, 121, 122, 22) and the insulating layers (11, 111, 21) covering the conductor layers (102, 12, 121, 122, 22). Further, the upper surfaces of the insulating layers (11, 111, 21) are roughened in order to improve adhesion to the conductor layers (121, 122, 12, 22) formed thereon. The covering layer formed on the surfaces of the conductor layers and the upper surfaces of the insulating layers, which are roughened, are described in detail with reference to an enlarged view of
The covering layer(CT) is formed of, for example, a material that bonds to both an organic material such as a resin forming the resin insulating layers (11, 111) and an inorganic material such as a metal forming the conductor layers (121, 122). The covering layer (CT) improves adhesion of the conductor layers (121, 122) to the insulating layers (111, 11) formed thereon. An example of a material used for the covering layer (CT) is a silane coupling agent containing an azole silane compound such as a triazole compound.
For example, in a case where high-frequency signals are transmitted via the conductor layers (121, 122), when the adhesion to the resin insulating layers (111, 11) is improved by roughening the surfaces of the conductor layers (121, 122), transmission characteristics of high-frequency signals may be degraded due to influence of a skin effect.
By improving the adhesion of the conductor layers (121, 122) to the resin insulating layers (111, 11) by the covering layer (CT) without roughening the conductor layers (121, 122), it may be possible to improve the transmission characteristics of high frequency signals of the conductor layers (121, 122).
As illustrated, the upper surfaces of the resin insulating layers (11, 111) are roughened. Specifically, as will be described later regarding the method for manufacturing a wiring substrate, in particular, the upper surface of the first resin insulating layer 111 is roughened to a desirable degree from a point of view of the adhesion to the conductor layer 122. For example, the roughened upper surface of the first resin insulating layer 111 has a surface roughness of about 0.03 μm-1.0 μm in arithmetic mean roughness. The adhesion between the resin insulating layer 111 and the second conductor layer 122 is improved, and a risk that a defect such as peeling may occur is reduced.
Further, in particular, inner sides of openings (13a) formed in the first resin insulating layer 111 are in a desirable state from a point of view of suppressing occurrence of a short circuit in the first conductor layer 121. Specifically, as illustrated in
When the gap (sp) extending from the peripheral edge of the bottom part of the opening (13a) has a relatively large dimension along the upper surface of the first conductor layer 121, the conductor filling the gap (sp) may be close to an adjacent pattern of the first conductor layer 121, and there may be an increased risk that a short circuit between conductor patterns may occur. From a point of view of suppressing such a short circuit, the dimension of the gap (sp) at the bottom part of the opening (13a) is preferably kept relatively small, and is preferably 1.0 μm or less.
Specifically, as will be described later regarding the method for manufacturing a wiring substrate, a desirable roughness of the upper surface of the first resin insulating layer 111 from a point of view of adhesion to the second conductor layer 122 and a desirable state of the openings (13a) (for example, a desirable state from a point of view of residue removal and short-circuit suppression) are achieved by roughening the upper surface of the first resin insulating layer 111 before forming the openings (13a).
With reference to
Next, as illustrated in
Subsequently, as illustrated in
The formation of the first resin insulating layer 111 on the first conductor layer 121 and the formation of the second conductor layer 122 on the first resin insulating layer 111 illustrated in
Subsequent to the state illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
After the formation of the openings (13a) using laser, in the state in which the protective layer (PT) is formed on the upper surface of the first resin insulating layer 111, a desmear treatment may be performed in which resin residues that remain in the openings (13a) are removed. As the desmear treatment in the openings (13a), preferably, a dry treatment may be carried out, for example, a plasma treatment using CF4 or CF4+O2, or a treatment using corona discharge may be performed. When the desmear treatment is being performed, the upper surface of the first resin insulating layer 111 is covered by the protective layer (PT). Therefore, influence due to the desmear treatment on the upper surface of the first resin insulating layer 111 is prevented, and the roughness illustrated in
As illustrated in
Following the formation of the openings (13a) using laser and the desmear treatment on the inner surfaces of the openings (13a), the inner surfaces of the openings (13a) may be subjected to ultrasonic cleaning. In the formation of the openings (13a), for example, laser ablation of a resin material forming the first resin insulating layer 111 may cause filler particles that are contained in the resin to fall off and remain in the openings. Such residues such as filler particles that remain in the openings (13a) may be removed by ultrasonic cleaning.
In the formation of the openings (13a), when excimer laser or the like that relatively suppresses residues remaining in the openings (13a) is used, it may be also possible that, after the formation of the openings (13a), ultrasonic cleaning is performed without performing a desmear treatment. It is also possible that the above-described formation of the openings (13a) in the first resin insulating layer 111, desmear treatment on the inner surfaces of the openings (13a), and ultrasonic cleaning are performed in a state in which the above-described protective layer (PT) is not provided on the upper surface of the first resin insulating layer 111, and the upper surface of the first resin insulating layer 111 is exposed. In particular, when the desmear treatment is performed in a dry manner, influence of the desmear treatment on the upper surface of the first resin insulating layer 111 is relatively small, and even when the protective layer (PT) is not provided, it may be possible that the upper surface of the first resin insulating layer 111 is maintained as a rough surface in a desirable state.
After the ultrasonic cleaning treatment on the inner surfaces of the openings (13a) is completed, as illustrated in
The metal film (12a) also fills the gap (sp) that occurs at the peripheral edge of the bottom part of each of the openings (13a). When the dimension (ex) (see
Next, as illustrated in
Next, the covering layer (CT) is formed on the upper and side surfaces of the second conductor layer 122. For example, by exposure and development of a photosensitive material, a resist film (not illustrated in the drawings) is formed covering a region excluding a region where the covering layer (CT) is to be formed, and the covering layer (CT) is formed covering a portion that is not covered by the resist film. The covering layer (CT) is formed, for example, by immersion in or spraying a liquid containing a material that bonds to both an organic material and an inorganic material, such as a silane coupling agent. Next, the resist film is removed, and the formation of the second conductor layer 122 of which the surface is covered by the covering layer (CT) is completed. Also in the formation of the first conductor layer 121 described above, a covering layer (CT) may be formed in a similar process. In the above, an example is described in which the covering layer (CT) is formed on the first conductor layer 121 and the second conductor layer 122. However, it is also possible that the method for manufacturing a wiring substrate of the present embodiment does not include the formation of the covering layer (CT). It is also possible that the covering layer (CT) is not formed on the surfaces of the first and second conductor layers (121, 122), and the electrolytic plating film (12b) of each of the first and second conductor layers (121, 122) is in contact with the insulating layer on the electrolytic plating film (12b).
In the method for manufacturing a wiring substrate of the present embodiment, the upper surface of the first resin insulating layer 111 is formed to be a rough surface having a good degree of surface roughness from a point of view of the adhesion to the second conductor layer 122, and formed such that the second conductor layer 122 and the first resin insulating layer 111 have relatively high adhesion to each other. On the other hand, the inner surfaces of the openings (13a) formed in the first resin insulating layer 111 may be subjected to a desmear treatment under desirable conditions from a point of view of residue removal. Further, the dimension (ex) (see
In other words, according to the method for manufacturing a wiring substrate of the present embodiment, by subjecting the upper surface of the first resin insulating layer 111 to a roughening treatment before the formation of the openings (13a), good adhesion between the first resin insulating layer 111 and the second conductor layer 122 is realized, and at the same time, the inner surfaces of the openings (13a) are in a good state from a point of view of residue removal. In addition, suppression of a short circuit in the first conductor layer 121 is also be realized. When the roughening of the upper surface of the first resin insulating layer 111 and the desmear treatment on the inner surfaces of the openings (13a) are performed at the same time after the formation of the openings (13a), it may be difficult to achieve a desirable degree of the roughening of the upper surface and a desirable degree of the desmear treatment on the inner surfaces of the openings (13a), and a relatively large gap (sp) may occur. Comparing to this, in the present embodiment, the roughening on the first resin insulating layer 111 may be performed under desirable conditions from a point of view of adhesion without adversely affecting the inner surfaces of the openings (13a). On the other hand, the treatment on the inner surfaces of the openings (13a), when necessary, may be performed under desirable conditions from a point of view of residue removal and short circuit suppression. Subsequently, as illustrated in
Next, as illustrated in
A method for manufacturing a wiring substrate according to an embodiment of the present invention is not limited the method described with reference to the drawings. In the manufacturing method of the present embodiment, at least, the first conductor layer 121, the first resin insulating layer 111, and the second conductor layer 122 are formed, and in the formation process thereof, it is sufficient when the roughening treatment on the upper surface of the first resin insulating layer 111 is performed before the formation of the openings (13a) in the first resin insulating layer 111. Therefore, a wiring substrate manufactured using the manufacturing method of the embodiment is not limited to the mode in which the first and second build-up parts (10, 20) are formed on both sides of the core substrate 100. It is also possible that the formation of the core substrate 100 and the formation of the second build-up part 20 are omitted. For example, in the method for forming the first and second conductor layers (121, 122) and the other conductor layers (102, 12, 22) of the wiring substrate 1, the formation of the covering layer (CT) may be omitted. Further, the region where the covering layer (CT) is formed is not limited to the upper and side surfaces of the conductor patterns. The covering layer may also be formed on an upper surface of an insulating layer. In the method for manufacturing a wiring substrate of the embodiment, the conditions, order, and the like of the manufacturing method described above may be changed as appropriate, except for the order of the roughening treatment with respect to the first resin insulating layer 111 and the formation of the openings (13a). Depending on a structure of an actually manufactured wiring substrate, some of the processes may be omitted, or other processes may be added.
Japanese Patent Application Laid-Open Publication No. 2001-85837 describes a method for manufacturing a multilayer printed wiring board. After an opening for a via hole is formed in an interlayer resin insulating layer formed on a conductor circuit, an inner wall of the opening and a surface of the interlayer resin insulating layer are treated with an oxidizing agent to form roughened surfaces.
In the method for manufacturing a printed wiring board described in Japanese Patent Application Laid-Open Publication No. 2001-85837, the roughening of the surface of the interlayer insulating layer and the roughening of the inner wall of the opening are performed at the same time using an oxidizing agent. It is thought that it is difficult to achieve both a desirable state (for example, a degree of roughening) on the surface of the interlayer insulating layer and a desirable state in the opening.
A method for manufacturing a wiring substrate according to an embodiment of the present invention includes: forming a first conductor layer and a first resin insulating layer that covers the first conductor layer; forming an opening that penetrates the first resin insulating layer and exposes the first conductor layer; and forming a via conductor in the opening and forming a second conductor layer in contact with an upper surface of the first resin insulating layer. The upper surface of the first resin insulating layer is subjected to a roughening treatment before the forming of the opening.
According to an embodiment of the present invention, a desirable rough surface is formed on the upper surface of the first resin insulating layer, and a desirable state in the opening is achieved. A highly reliable wiring substrate is provided in which good adhesion between a resin insulating layer and a conductor layer is realized, and at the same time, a via conductor formed in a good state in an opening is realized.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-146038 | Sep 2021 | JP | national |
