"A Practical Trench Isolation Technology with a Novel Planarization Process" by G. Fuse, et al, IEDM 87, pp. 732-735. |
"A New Isolation Method with Boron-Implanted Sidewalls for Controlling Narrow-Width Effect", IEEE Transactions on Electron Devices, vol. ED-34, No. 2, Feb. 1987, pp. 356-360. |
"A Variable Size Shallow Trench Isolation (STI) Technology with Diffused Sidewall Doping for Submicron CMOS" by B. Davari et al, IEDM 88, pp. 92-95. |
"Trench Etches in Silicon with Controllable Sidewall Angles" by Robert N. Carlile, et al, Journal of Electrochemical Society: Solid-State Science and Technology, Aug. 1983, pp. 2058-2064. |
"Buried-Oxide Isolation with Etch-Stop (BOXES)" by Robert F. Kwasnick, et al, IEEE Electron Device Letters, vol. 9, No. 2, Feb. 1988, pp. 62-64. |
"A New Trench Isolation Technology as a Replacement of LOCOS" by H. Mikoshiba, et al, IEDM 84, pp. 578-581. |
"Defect Generation in Trench Isolation" by Clarence W. Teng, et al, IEDM 84, pp. 586-589. |
"Latchup-Free CMOS Structure Using Shallow Trench Isolation" by Y. Nitsu, et al, IEDM 85, pp. 509-512. |
"A New Bird's-Beak Free Field Isolation Technology for VLSI Devices" by Kei Kurosawa et al, IEDM 81, pp. 384-387. |
"A Simplified Box (Buried-Oxide) Isolation Technology for Megabit Dynamic Memories" by T. Shibata et al, IEDM 83, pp. 27-30. |
"Trench Isolation Prospects for application in CMOS VLSI" by R. D. Rung, IEDM 84, pp. 574-577. |