Y. Hazuki et al., A New Application of Rie to Planarization and Edge Rounding of SiO.sub.2 Hole in the A1 Multilevel Interconnection, VLSI Sep. 82. |
Tom Abraham, Reactive Facet Tapering of Plasma Oxide for Multilevel Interconnect Applications, V-MIC Conf. Jun. 87. |
E. J. McInerney, AN IN-SITU Planarized PECVD Silicon Dioxide Interlayer Dielectric, V-MIC Conf., Jun. 86. |
G. E. Gimpelson et al., Plasma Planarization with a Non-Planar Sacrificial Layer, V-MIC Conf., Jun. 84. |
T. Abraham, Sidewall Tapering of Plasma Etched Metal Interconnects, V-MIC Conf., Jun. 86. |
Barbara Vasquez, Planarized Oxide with Sacrificial Photoresist: Etch Rate Sensitivity to Pattern Density, V-MIS Conf., Jun. 87. |
H. Kotami et al., Sputter-Etching Planarization for Multilevel Metallization, J. Electrochem. Soc., p. 645, Mar. 1983. |