Claims
- 1. A method for polishing a semiconductor wafer, characterized by preparing a finished backing pad by the steps comprising:
- a. fixing a backing pad blank on a carrier plate with a wafer-holding surface thereof laid upwards and surface grinding the wafer-holding surface of said backing pad blank with a precision surface grinder until said wafer-holding surface has a flatness such that the difference between a maximum and a minimum, (TV.sub.5,) of thickness of said backing pad measured at a total of five points, i.e. one point at the center thereof and four points at an inward distance of 5 mm from terminals of two perpendicularly intersecting diameters thereof, after one minute's exertion thereto of a load of 300 gf/cm.sup.2, is not more than 1 .mu.m,
- b. placing said semiconductor wafer on a wafer holding jig having a template containing at least one wafer-positioning hole fixed on a carrier plate in such a manner that said backing pad enters said positioning hole; and
- c. polishing said semiconductor wafer.
- 2. A method according to claim 1, wherein a gap in the range of from 0.5 to 1.5 mm is interposed between an inner edge of said wafer-positioning hole of said template and an outer edge of said backing pad.
CROSS REFERENCE TO A RELATED APPLICATION
This is a divisional of co-pending application Ser. No. 07/688,108, filed Apr. 19, 1991, now U.S. Pat. No. 5,102,602.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
5096854 |
Saito et al. |
Mar 1992 |
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Divisions (1)
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Number |
Date |
Country |
Parent |
688108 |
Apr 1991 |
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