METHOD FOR PREPARING LOW-WARPAGE SEMICONDUCTOR SUBSTRATE

Abstract

Disclosed is a method for preparing a low-warpage semiconductor substrate. The method includes: providing a first substrate and a second substrate, the first substrate including a first surface and a second surface which are opposite to each other, a first insulating layer is disposed on the first surface. A second insulating layer is disposed on the second surface. The second substrate includes a support layer, an oxidation layer arranged on a surface of the support layer, and a device layer arranged on a surface of the oxidation layer. The method further includes bonding the first substrate and the second substrate by using the device layer and the first insulating layer as an intermediate layer; and forming a passivation layer on a surface of the second insulating layer by means of adhesion, where the second insulating layer and the passivation layer are configured to adjust warpage of the semiconductor substrate.

Description

TECHNICAL FIELD

The present disclosure relates to methods for preparing silicon substrates on insulators, and in particular, relates to a method for preparing a low-warpage semiconductor substrate.

BACKGROUND

During the preparation process of a silicon-on-insulator (SOI) wafer, an oxidation layer on a surface of a device layer needs to be corroded. In addition, an insulating layer supporting a back side of a substrate is removed during the process of corrosion the oxidation layer, which results in that warpage of a silicon wafer is great. As illustrated in FIG. 1A, a first surface of a support substrate 100 is provided with a device layer 110 and an oxidation layer 120 located above the device layer 110; a second surface of the support substrate 100 opposite to the first surface thereof is provided with an insulating layer 130; when the oxidation layer 120 is removed by means of corrosion, the corrosion liquid sputters or flows, which may cause the insulating layer 130 to be removed because of the corrosion. As a result, the warpage of the semiconductor substrate is great. FIG. 1B is a transmission electron microscope diagram of a bonded SOI wafer in the related art. It can be seen from FIG. 1B that an inclination angle of the semiconductor substrate is great after the oxidation layer 120 is removed, which indicates that the warpage of the semiconductor substrate is great. A great warpage of the semiconductor substrate may result in such circumstances as component failure, and occurrence of fragments during the preparation process of the semiconductor substrate, which causes yield loss. Therefore, a user desires a low-warpage semiconductor substrate.

SUMMARY

A technical problem to be solved in the present disclosure is to provide a method for preparing a low-warpage semiconductor substrate. This method is capable of reducing warpage of a wafer.

To this end, the present disclosure provides a method for preparing a low-warpage semiconductor substrate. The method includes: providing a first substrate and a second substrate, the first substrate including a first surface and a second surface which are opposite to each other. The first surface is provided with a first insulating layer disposed on the first surface. The second surface is provided with a second insulating layer disposed on the second surface. The second substrate includes a support layer, an oxidation layer arranged on a surface of the support layer, and a device layer arranged on a surface of the oxidation layer. The method includes bonding the first substrate and the second substrate by using the device layer and the first insulating layer as an intermediate layer. The method also includes forming a passivation layer on a surface of the second insulating layer by means of adhesion, where the second insulating layer and the passivation layer are configured to adjust warpage of the semiconductor substrate.

The present disclosure is advantageous in that a passivation layer is adhered on the surface of the second insulating layer, and the passivation layer is capable of preventing the second insulating layer from corrosion and thus capable of effectively reducing warpage of the wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic process diagram of removing an oxidation layer by means of corrosion during the preparation of a SOI wafer in the related art;

FIG. 1B is a transmission electron microscope of a bonded SOI wafer in the related art;

FIG. 2 is a schematic diagram of steps of a method for preparing a low-warpage semiconductor substrate according to one or more embodiments of the present disclosure;

FIG. 3A to FIG. 3E are schematic diagrams of an implementation process according to one or more embodiments of the present disclosure;

FIG. 4 is a transmission electron microscope of a semiconductor substrate prepared by using the method according to the present disclosure; and

FIG. 5 is a comparison of warpage of a semiconductor substrate prepared by using the method of the present disclosure, and warpage of a semiconductor substrate prepared by using a conventional method in the related art.

DETAILED DESCRIPTION

Embodiments illustrating a method for preparing a low-warpage semiconductor substrate according to the present disclosure are described in detail with reference to the accompanying drawings.

The terminology used in the present disclosure is for the purpose of describing exemplary embodiments only and is not intended to limit the present disclosure. As used in the present disclosure and the appended claims, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It shall also be understood that the terms “or” and “and/or” used herein are intended to signify and include any or all possible combinations of one or more of the associated listed items, unless the context clearly indicates otherwise.

It shall be understood that, although the terms “first,” “second,” “third,” etc. may include used herein to describe various information, the information should not be limited by these terms. These terms are only used to distinguish one category of information from another. For example, without departing from the scope of the present disclosure, first information may include termed as second information; and similarly, second information may also be termed as first information. As used herein, the term “if” may include understood to mean “when” or “upon” or “in response to” depending on the context.

Reference throughout this specification to “one embodiment,” “an embodiment,” “exemplary embodiment,” or the like in the singular or plural means that one or more particular features, structures, or characteristics described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment,” “in an exemplary embodiment,” or the like in the singular or plural in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics in one or more embodiments may include combined in any suitable manner.

FIG. 2 is a schematic diagram of steps of a method for preparing a low-warpage semiconductor substrate according to one or more embodiments of the present disclosure. The method includes the following steps. In step S21, providing a first substrate and a second substrate, the first substrate including a first surface and a second surface which are opposite to each other, disposing a first insulating layer on the first surface, disposing a second insulating layer on the second surface, and the second substrate including a support layer, an oxidation layer arranged on a surface of the support layer and a device layer arranged on a surface of the oxidation layer. In step S22, bonding the first substrate and the second substrate by using the device layer and the first insulating layer as an intermediate layer. In step S23, annealing the bonded substrate. In step S24, thinning the second substrate to remove the support layer. In step S25, forming a passivation layer on a surface of the second insulating layer by means of adhesion, the second insulating layer and the passivation layer being configured to adjust warpage of the semiconductor substrate. In step S26, corroding the substrate to remove the oxidation layer.

As illustrated in FIG. 3A, with reference to step S21, a first substrate 310 and a second substrate 320 are provided, where the first substrate 310 includes a first surface and a second surface which are opposite to each other, the first surface being provided with a first insulating layer 330, the second surface being provided with a second insulating layer 380; and the second substrate 320 includes a support layer 340, an oxidation layer 350 arranged on a surface of the support layer 340 and a device layer 360 arranged on a surface of the oxidation layer 350.

The first substrate 310 and the second substrate 320 may be lightly-doped or heavily-doped Si substrates, or may be p-type or n-type doped substrate, where the dopant may be B, P, As or other dopant elements. In particular, the second substrate may be used as a support substrate of a finally formed semiconductor substrate, which may be prepared by using materials within a more extensive range, even not limited to a semiconductor substrate.

The first insulating layer 330 and the second insulating layer 380 are independently made from any one of silicon oxide, silicon nitride and silicon oxynitride. The formation process may employ a chemical vapor deposition or thermal oxidation. In particular with respect to a monocrystalline silicon substrate, a silica insulating layer is formed by preferably using the thermal oxidization.

The device layer 360 may be formed by means of epitaxy. The epitaxy may be a homoepitaxy or an isoepitaxy, and the homoepitaxy is preferably used to achieve a higher crystal quality, for example, the device layer 330 having an epitaxy monocrystalline silicon on the surface of the first substrate made from a monocrystalline silicon. The oxidation layer 350 may be formed by means of ion injection, and is present in the second substrate 320 as a buried oxidation layer.

Further, as an optional step, upon this step S21, the method may further include a step of forming an insulating layer on the surface of the device layer 360; and in the bonding step, the first substrate and the second substrate are bonded by using the insulating layer on the surface of the device layer 360 and the first insulating layer 330 as an intermediate layer.

As illustrated in FIG. 3B, with reference to step S22, the first substrate 310 and the second substrate 320 are bonded by using the device layer 360 and the first insulating layer 330 as an intermediate layer. The bonding herein may be common hydrophilic bonding or hydrophobic bonding, or may be plasma assistant hydrophilic bonding, preferably the hydrophilic bonding and the plasma assistant hydrophilic bonding.

With reference to step S23, the bonded substrate is annealed. By means of annealing, a covalent bond is formed at the bonding interface, which enhances the bonding force. The annealing temperature is higher than 900° C., the annealing duration is longer than 2 hours, and the annealing atmosphere is wet oxygen, dry oxygen, nitrogen or oxygen-argon mixture gas.

As illustrated in FIG. 3C, with reference to step S24, the second substrate 320 is thinned to remove the support layer 340. The step of thinning the first substrate 310 may employ a method of firstly grinding and then polishing. The grinding refers to coarsely grinding the first substrate 310 firstly and then finely grinding the first substrate 310. The first substrate is quickly thinned by means of coarse grinding, and damages caused by the grinding to the first substrate 310 are reduced by means of fine grinding. The polishing may employ chemical-mechanical polishing to conduct single-face polishing or double-face polishing, where the single-face polishing is preferably employed to prevent the insulating layer 380 from being removed.

Further, if a chamfering is needed, before step S24, a chamfering process may be performed for the bonded substrate.

As illustrated in FIG. 3D, in step S25, a passivation layer 370 is formed on a surface of the second insulating layer 380 by means of adhesion, to prevent the second insulating layer 380 from corrosion. In the subsequent corrosion step, the passivation layer 370 may not be corroded by the corrosion liquid, and the corrosion liquid may not corrode the first insulating layer 330, such that a low-warpage semiconductor substrate may be obtained.

In the present disclosure, the passivation layer may be adhered by using, but not limited, to the following steps:

(1) placing the thinned substrate on a working table;

(2) making the face to be adhered with a film face, i.e., the second insulating layer 380, upwards, and taking out a blue type which has the same size as the substrate; and

(3) during tearing-off of the film, tightly adhering the film onto the second insulating layer 380 of the substrate by using a slider bar.

As illustrated in FIG. 3E, in step S26, a corrosion step is performed for the substrate to remove the oxidation layer 350. In this step, the oxidation layer 350 is removed by means of corrosion to expose the device layer 360. When the substrate is corroded by using the corrosion liquid to remove the oxidation layer 350, although the corrosion liquid may sputter or flow to the bottom of the substrate, with the presence of the passivation layer 370 at the bottom of the substrate, the second insulating layer 380 would not be corroded by the corrosion liquid. In this way, a low-warpage semiconductor substrate is provided. If the oxidation layer 350 is silica, the corrosion liquid is preferably HF for corrosion.

FIG. 4 is a transmission electron microscope of a semiconductor substrate prepared by using the method according to the present disclosure. As seen from FIG. 4, after the oxidation layer 350 is removed, compared with the related art, an inclination angle of the semiconductor substrate becomes smaller, which indicates that the warpage of the semiconductor substrate becomes smaller. FIG. 5 is a comparison of warpage of a semiconductor substrate prepared by using the method of the present disclosure, and warpage of a semiconductor substrate prepared by using a conventional method in the related art. As seen from FIG. 5, since the passivation layer 370 is formed on the surface of the second insulating layer 380 according to the present disclosure, the second insulating layer 380 is not corroded by the corrosion liquid. Therefore, the warpage of a semiconductor substrate prepared by the method of the present disclosure is smaller than that of a semiconductor substrate prepared by using a conventional method in the related art.

Here, the passivation layer may be a blue type, and the first insulating layer and the second insulating layer are independently made from any one of silicon oxide, silicon nitride and silicon oxynitride. Further, upon the bonding step, the method may further include a step of annealing the bonded substrate. Upon the bonding step, the method may further include a step of thinning the second substrate to remove the support layer. Upon the thinning step, the method may further include a corrosion step to remove the oxidation layer. The thinning step employs one or both of mechanical grinding and chemical-mechanical polishing. Upon the bonding step, the method may further include a step of chamfering the second substrate and the first insulating layer.

Described above are examples of the present disclosure. It should be noted that persons of ordinary skill in the art may derive other improvements or polishments without departing from the principles of the present disclosure. Such improvements and polishments shall be deemed as falling within the protection scope of the present disclosure.

Claims

1. A method for preparing a low-warpage semiconductor substrate, comprising: providing a first substrate and a second substrate, the first substrate comprising a first surface and a second surface which are opposite to each other, disposing a first insulating layer on the first surface, disposing a second insulating layer on the second surface, wherein the second substrate comprises a support layer, an oxidation layer arranged on a surface of the support layer, and a device layer arranged on a surface of the oxidation layer;bonding the first substrate and the second substrate by using the device layer and the first insulating layer as an intermediate layer;forming a passivation layer on a surface of the second insulating layer by means of adhesion, the second insulating layer and the passivation layer being configured to adjust warpage of the semiconductor substrate.

2. The method for preparing the low-warpage semiconductor substrate according to claim 1, wherein the passivation layer is a blue type, and the first insulating layer and the second insulating layer are independently made from any one of silicon oxide, silicon nitride and silicon oxynitride.

3. The method for preparing the low-warpage semiconductor substrate according to claim 1, further comprising annealing the bonded substrate after bonding the first substrate and the second substrate.

4. The method for preparing a low-warpage semiconductor substrate according to claim 1, further comprising thinning the second substrate to remove the support layer after bonding the first substrate and the second substrate.

5. The method for preparing a low-warpage semiconductor substrate according to claim 4, wherein upon the thinning step, the method further comprises a corrosion step to remove the oxidation layer.

6. The method for preparing a low-warpage semiconductor substrate according to claim 4, wherein the thinning step employs one or both of mechanical grinding and chemical-mechanical polishing.

7. The method for preparing a low-warpage semiconductor substrate according to claim 1, wherein upon the bonding step, the method further comprises a step of chamfering the second substrate and the first insulating layer.