Patent Application
20200118479
The present invention relates to display technology, more particularly, to a method of processing image data with enhanced grayscale level for displaying image on a display panel, a processor that implements the method, and a display apparatus having the same.
A display panel, for example a liquid-crystal display (LCD) panel, includes at least a timing controller and a driver circuit. The tuning controller is configured to convert the image data to a format that meets timing requirement of the driver circuit. The driver circuit selectively controls each subpixel brightness (or grayscale level) to display a certain image based on a driving signal provided from the timing controller. Accordingly, the grayscale level of the display panel is limited by the chip adopted in the driver circuit. A conventional driving chip has maximum data bandwidth of 12-bit, which normally yields grayscale levels up to 4096 for the image displayed by the display panel.
Normally, in order to increase grayscale levels of the image displayed on the display panel, the data bandwidth of the driving chip must be increased, which requires that the chip must transmit data with faster rate. While the data bandwidth is limited by the (transistor) circuit integration on the chip and is determined by overall development of semiconductor technology. Therefore, simple request on increasing the data bandwidth is translated to high dependency on higher-density of circuit integration or increasing number of digital to analog converters or larger chip area which results directly to higher cost in making the driving chip.
In an aspect, the present disclosure provides a method for processing image data with enhanced grayscale level for a display panel. The method includes receiving image data with (M+N)-bit maximum grayscale level. Additionally, the method includes dividing the image data of the (M+N)-bit to a first set of data with M-bit and a second set of data with N-bit. The method further includes reconstructing K sets of new image data with grayscale levels up to N-bit based on the first set of data and the second set of data. Furthermore, the method includes forwarding the K sets of new image data to a driver circuit respectively in corresponding K divisional time periods defined by a timing controller. Moreover, the method includes driving the display panel to display image in the corresponding K divisional time periods respectively using the K sets of new image data. M is an integer equal to or greater than 2. N is an integer equal to or greater than 8, K is equal to 2M. M is less than N.
Optionally, the first set of data includes low-order part M-bit data of the image data with (M+N)-bit and the second set of data includes high-order part N-bit data of the image data with (M+N)-bit.
Optionally, the N-bit is selected from 8-bit, 10-bit, and 12-bit, and M is equal to 2.
Optionally, the first set of data includes three first subsets of data respectively for a subpixel of a first color, a subpixel of a second color, and a subpixel of a third color. Each of the three first subsets of data includes 0, 1, 2, and 3.
Optionally, the second set of data includes three second subsets of data respectively for the subpixel of the first color, the subpixel of the second color, and the subpixel of the third color. Each of the three second subsets of data includes grayscale values up to 2N equal to 256, 1024, and 4096 respectively for the driver circuit for the display panel capable of handling 8-bit, 10-bit, and 12-bit of image data.
Optionally, the reconstructing the K sets of new image data includes setting one of the three second subsets of data as a same base for each of the K sets of new image data for one of the subpixel of the first color, the subpixel of the second color, and the subpixel of the third color; determining K adjustments respectively for the K sets of new image data from the three first subsets of data; and adding the K adjustments to the same base to obtain the K sets of new image data.
Optionally, the determining the K adjustments includes breaking each of three first subsets of data up to M-bit to K elements with values of sub-M-bit data, limiting a sum of the K elements equal to a value of M-bit data, and redistributing the K elements into one row of a three-row matrix.
Optionally, the redistributing the K elements further includes shuffling elements in each row of the three-row matrix to achieve optimal element diversities thereof to have one or more optimal combinations of the K elements, and selecting the K elements in the one or more optimal combinations to be respective K adjustments.
Optionally, the reconstructing the K sets of new image data includes selecting K=22=4 sets of new image data separately being sent from the driver circuit to the display panel via 4 lanes of the timing controller under Mobile Industry Processor Interface (MIPI) display serial interface.
In another aspect, the present disclosure provides a display apparatus including a display panel, a driver circuit for driving image display on the display panel, and a timing controller coupled to the driver circuit. The timing controller is configured to receive image data with a maximum grayscale level up to (M+N)-bit. Additionally, the timing controller is configured to divide the image data to a first set of data with M-bit and a second set of data with N-bit. The timing controller is further configured to reconstruct K sets of new image data with grayscale levels up to N-bit based on the first set of data and the second set of data. Furthermore, the timing controller is configured to forward the K sets of new image data to the driver circuit respectively in corresponding K divisional time periods defined by the timing controller of the display panel. M is an integer equal to or greater than 2. N is an integer equal to or greater than 8, K is equal to 2M. M is less than N.
Optionally, the first set of data includes low-order part M-bit data of the image data with (M+N)-bit, and the second set of data includes high-order part N-bit data of the image data with (M+N)-bit.
Optionally, the N-bit is selected from 8-bit, 10-bit, and 12-bit, and M is equal to 2.
Optionally, the first set of data includes three first subsets of data respectively for a subpixel of a first color, a subpixel of a second color, and a subpixel of a third color. Each first subset of data includes 0, 1, 2, and 3.
Optionally, the second set of data includes three second subsets of data respectively for the subpixel of the first color, the subpixel of the second color, and the subpixel of the third color. Each second subset of data includes grayscale values up to 2N equal to 256, 1024, and 4096 respectively for the driver circuit for the display panel capable of handling 8-bit, 10-bit, and 12-bit of image data.
Optionally, the timing controller is configured to reconstruct the K sets of new image data by setting one of the three second subsets of data as a same base for each of the K sets of new image data for one of the subpixel of the first color, the subpixel of the second color, and the subpixel of the third color. Further, the timing controller is configured to reconstruct the K sets of new image data by determining K adjustments respectively for the K sets anew image data from the three first subsets of data. Furthermore, the timing controller is configured to reconstruct the K sets of new image data by adding the K adjustments to the same base to obtain the K sets of new image data.
Optionally, each of the K adjustments includes one of K elements of sub-M-bit as an additive constitution of a value of M-bit associated with each of three first subsets of data, the K elements being assigned to corresponding K spatial locations in one row of a three-row matrix.
Optionally, the display apparatus further includes one or more selectors configured to shuffle the K elements in each row of the three-row matrix to achieve optimal element diversities thereof to have one or more optimal combinations of the K elements, and to select the K elements in the one or more optimal combinations to be respective K adjustments.
Optionally, the K sets of new image data includes K=22=4 sets of new image data separately being sent from the driver circuit to the display panel via 4 lanes of the timing controller under Mobile Industry Processor Interface (MIPI) display serial interface.
For the display apparatus described herein, where the driver circuit coupled to the timing controller is configured to receive four sets of new image data of N-bit generated by the timing controller based on image data of (N+2)-bit via four lanes in a time period. In an example, the four sets of new image data of N-bit are sent via four lanes in four divisional time periods. As a result, the transmission rate of the image data in each lane is four times of a normal rate. The display panel is configured to use the four sets of new image data to display image in the normal rate.
Optionally, the display panel is a LCD panel configured to handle image data of N=8, 10, or 12-bit.
In yet another aspect, the present disclosure provides a non-transitory tangible computer-readable storage medium storing computer-readable instructions. The computer-readable instructions are executable by a processor to cause the processor to perform receiving image data with a maximum grayscale level up to (M+N)-bit for a display panel. Additionally, the computer-readable instructions are executable by a processor to cause the processor to perform dividing the image data of (M+N)-bit to a first set of data including low-order part with M-bit and a second set of data including high-order part up to N-bit.
Furthermore, the computer-readable instructions are executable by a processor to cause the processor to perform reconstructing K=2M sets of new image data up to N-bit based on the first set of data and the second set of data. Moreover, the computer-readable instructions are executable by a processor to cause the processor to perform forwarding K sets of new image data to the driver circuit respectively in corresponding K divisional time periods defined by a timing controller of the display panel.
The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present invention.
The disclosure will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of some embodiments are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
A display panel includes mainly a timing controller and a driver circuit. The timing controller is configured to convert the image data to a format that meets timing requirement of the driver circuit. The driver circuit is configured to selectively control each subpixel brightness (or grayscale level) to display an image based on a driving signal provided from the timing controller based on the image data. Accordingly, the maximum grayscale level that can be achieved by the display panel is limited by IC chip adopted by the driver circuit of the display panel. Normally, existing IC chip for the driver circuit has a 12-bit capacity of data bandwidth, yielding grayscale levels up to 4096 for the image displayed by the display panel. For displaying image with higher grayscale levels, the data bandwidth must be increased in the corresponding IC chip for the driver circuit. This demands higher bit-rate for transferring data through the driver circuit for driving the display panel. Higher bit-rate for IC chip means a requirement of forming more DAC/ADC circuits on the IC chip with higher integration density. This requires either building the driver circuit on larger chip area or relying on design with high integration density or high-level processing technology, all leading to much higher cost for integrating the driver circuit on the IC chip.
Accordingly, the present disclosure provides, inter alia, a method for processing image data with enhanced grayscale level for a display panel, a display apparatus, and non-transitory tangible computer-readable storage medium that substantially obviate one or more of the problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides a method for processing image data with enhanced grayscale level for a display panel. Optionally, the method is applicable to but not limited to a liquid crystal display (LCD) panel or an Organic Light-Emitting Diode (OLED) display panel. In some embodiments, the method includes receiving image data with a maximum grayscale level up to (M+N)-bit, i.e., M-bit higher than a regular maximum grayscale level of N-bit used by a driver circuit of the display panel: dividing the image data of (M+N)-bit to a first set of data containing low-order part up to M-bit and a second set of data containing high-order part up to N-bit; reconstructing K sets of new image data with grayscale levels up to N-bit based on the first set of data and the second set of data; forwarding the K sets of new image data to the driver circuit respectively in corresponding K divisional time periods defined by a timing controller of the display panel; and driving the display panel to display image in the K divisional time periods respectively using the K sets of new image data. Optionally, M is an integer equal to or greater than 2, N is an integer equal to or greater than 8, K is equal to 2M, and M is less than N. Typically, a maximum grayscale level can be handled in existing display panel is 8-bit, 10-bit, or 12-bit (i.e., N=8, 10, or 12). For example, one of a 14-bit data, 111 . . . 11101, is received. The high-order part with 12-bit of the 14-bit data is 111 . . . 111. The low-order part 2-bit data is 01, or simply with value 1. That is: M=2, N=12. Other low-order part 2-bit data includes 00, 01, 10, 11, corresponding to values of 0, 1, 2, and 3, respectively.
In the embodiment, the method is to use existing display panel with maximum data bandwidth of handling grayscale level up to N-bit to display image with enhanced grayscale level of (M+N)-bit. The step of dividing the image data of the method is to obtain the second set of data with grayscale levels up to the high-order part N-bit data of the (M+N)-bit data as a base data. In order to substantially fully characterize the enhanced grayscale level of (M+N)-bit image data using the N-bit base data, it needs at least K=2M variations of the base data that correspond to the image data intended for displaying the image with enhanced grayscale level of (M+N)-bit. So, the step of dividing the image data is also to obtain the first set of data with low-order part of M-bit for deducing adjustments to provide necessary variations of the base data. Thus, the step of reconstructing K sets of new image data is to generate the new image data. Firstly, the new image data are N-bit data that is able to be handled by the existing driver. Secondly, the new image data includes K=2M sets of variations for substantially providing full characteristics of enhanced grayscale levels of (M+N)-bit to the image displayed by the display panel.
In the embodiment, the K sets of new image data are directly generated based on the first set of data up to M-bit and the second set of data up to N-bit obtained in the step of dividing the original image data. The first set of data includes three first subsets of data of M-bit associated with a subpixel of a first color (e.g., red), a subpixel of a second color (e.g., green), and a subpixel of a third color (e.g., blue). The second set, of data includes three second subsets of data of N-bit respectively associated with the subpixel of the first color, the subpixel of the second color, and the subpixel of the third color. In particular, the step of reconstructing the K sets of new image data includes setting one of the three second subsets of data as a same base for each of the K sets of new image data associated with the first color, the the second color, and the third color. Then, the step further includes determining K adjustments respectively for the K sets of new image data from the three first subsets of data and adding the K adjustments to the same base to obtain the K sets of new image data. Here, K must be equal to 2M. For example, M=2, then K=22=4. 4 variations of N-bit data may possibly produce image display effect of the image data of (N+2)-bit. If M=3, then K must be 23=8. For typical existing display panel, a timing controller associated with the display panel has a built-in capability of handling four variations of the data at a time by design based on MIPI specification for the display panel. Thus, typically, K is chosen to be 4 and accordingly, M is 2.
In the embodiment, the step of determining K adjustments is executed by breaking each of three first subsets of data with M-bit to K elements of sub-M-bit with a limitation that a sum of the K elements is equal to the value of the M-bit data. For example, a 2-bit data value is 3 and K=4 elements can be 1, 1, 1, 0 with a sum of 1+1+1+0=3. The step further includes redistributing the K elements into one row of a three-row matrix. Additionally, the step of redistributing the K elements is executed by shuffling the elements in each row of the three-row matrix to achieve optimal element diversities thereof to have one or more optimal combinations of the K elements, and selecting the K elements in the one or more optimal combinations to be respective K adjustments. In a specific implementation of the method, the optimal element diversities can be achieved in more than one combination of the K elements while effectively, the K adjustments based on the selected. K elements with the optimal combination can be added to the base data respectively to produce necessary variations of the K sets of new image data.
In the embodiment, the method further includes forwarding the K sets of new image data to the driver circuit respectively in corresponding K divisional time periods defined by the timing controller of the display panel. For the existing display panel, the timing controller has a built-in four lanes under MIPI display serial interface (DSI) specification that can transfer data in time-divisional manner Thus, typically, K is chosen to be 4 and the four sets of new image data are separately forwarded to the driver circuit via the 4 lanes of the DSI interface in four divisional time periods per one display cycle (for one frame of image). The display panel then can be driven by the driver circuit to use the K=4 sets of new image data to display image in the four divisional time periods. Since K=2M, accordingly, M is 2. For advanced display panel, if the timing controller has more built-in selectors for handling selections of more elements out of the grayscale level up to 3-bit with capability of 8 lanes for transferring data in 8 divisional time periods, the K can be 8 and M can be 3. Below, examples in description and figures for illustrating the invention are only provided using M=2 and N=12.
In one aspect, the present disclosure provides a method of processing image data with enhanced grayscale level for displaying image on a display panel.
In the embodiment, instead of directly forwarding these image data from the timing controller to the driver circuit, a processor of the timing controller is configured to perform a step of the method for dividing the image data DXN+2 to a first set of data LX2 with grayscale levels up to 2-bit and a second set of data MXN with grayscale levels of 3-bit and higher up to N-bit. In particular, this step is performed for each of the three sets of data signals R[D-1:0], G[D-1:0], and 13[D-1:0] for three colors subpixels. X stands for each of R, G, and B three colors. Therefore, the first set of data LX2 in fact includes three subsets of data LR2, LG2, and LB2. Similarly, the second set of data MXN also includes three subsets of data MRN, MGN, and MBN.
Referring to
Referring to
Optionally, the determination of the four adjustments is executed by employing one or more selectors in the processor to select either 0 or LX2 itself for each adjustment. For example, the four adjustments are 3, 0, 0, and 0. Then the four sets of new image data are: SX1=MXN+N+3, SX2=MXN, SX3=MXN, and SX4=MXN, for any color X. Optionally, determining the four adjustments can be executed by employing one or more selectors to firstly break down the 2-bit of the first set of data LX2 to four elements ΔX1, ΔX2, ΔX3, and ΔX4 with grayscale level of 1-bit (i.e., 0 or 1) with a limitation that a sum of the four elements ΔX1+ΔX2+ΔX3+ΔX4 equals to LX2. For example, LX2=3 is broken down to 1, 1, and 1 so the four adjustments can be 1, 1, 1, and 0. The sum of the four elements 1+1+1+0 equals to 3. The four elements ΔX1, ΔX2, ΔX3, and ΔX4 with value of 1-bit are assigned to be four elements in one row of a three-row matrix. This applies for every color X=R, or G, or B so that total three rows of four elements respectively associated with 3 colors are assigned to construct a 3×4 matrix, Dis_array:
Secondly, the selector associated with the processor can be configured to shuffle the four elements with value of 1-bit in each row of the 3×4 matrix such that the matrix achieves optimal elements diversities. Optionally, such optimal element diversities may be satisfied in one or more combinations of shuffling the four elements, in each of three rows of the three-row matrix. The four adjustments for the four sets of new image data for one of three colors thus can be selected to be the four elements ΔX1, ΔX2, ΔX3, and ΔX4 of corresponding one row of the three-row matrix with optimal elements diversities. By adding the four adjustments to the base, the four sets of new image data SXn for the corresponding color X are obtained. Each set of new image data has maximum grayscale level of N-bit that the driver circuit is designed to handle for displaying image on the display panel.
Referring to
However, the above selection is certainly not spatially optimized as the first set of new image data is forced to add a higher grayscale level of 3 out of rest three sets of new image data at a normal grayscale. When the driver circuit uses these new image data to display an image, a viewer may easily capture abnormal color/brightness variation in certain subpixels, which is an undesired situation.
In another aspect, the present disclosure provides a display apparatus having a display panel; a driver circuit for driving image display in the display panel; and a timing controller coupled to the driver circuit. In some embodiments, the timing controller includes a memory; and one or more processors. The memory and the one or more processors are connected with each other. The memory stores computer-executable instructions for controlling the one or more processors to receive image data with a maximum grayscale level up to (M+N)-bit, M-bit higher than a regular maximum grayscale level of N-bit normally handled by the driver circuit of the display panel; divide the image data of (M+N)-bit to a first set of data with low-order part M-bit and a second set of data with high-order part N-bit of the (M+N)-bit data; reconstruct K sets of new image data with grayscale levels up to N-bit based on the first set of data and the second set of data; and forward the K sets of new image data to the driver circuit respectively in corresponding K divisional time periods defined by the timing controller of the display panel. Various appropriate memories may be used in the present apparatus. Examples of appropriate computer readable memories include, but are not limited to, magnetic disk or tape, optical storage media such as compact disk (CD) or DVD (digital versatile disk), flash memory, and other non-transitory media. Optionally, the memory is a non-transitory memory. Optionally, M is an integer equal to or greater than 2, N is an integer equal to or greater than 8, K is equal to 2M, and M is less than N.
In some embodiments, the timing controller is configured to receive image data with a maximum grayscale level up to (N+2)-bit, 2-bit higher than a regular maximum grayscale level of N-bit normally handled by the driver circuit of the display panel. Further, the timing controller is configured to divide the image data to a first set of data of 2-bit and a second set of data up to N-bit. Additionally, the timing controller is configured to reconstruct multiple sets of new image data of N-bit based on the first set of data and the second set of data. Furthermore, the timing controller is configured to forward the K sets of new image data to the driver circuit respectively in corresponding multiple divisional time periods defined by the timing controller of the display panel. Once each of the K sets of new image data is sent to the driver circuit, the driver circuit is able to use the new image data of N-bit to display an image on the display panel in a corresponding one time period. When all the K sets of new image data are displayed in fill cycle (transmitted in the time period with a rate of K-times of a normal rate) of one display cycle, the display panel effectively display an image with enhanced grayscale level up to (N+2)-bit.
In the embodiment, the K sets of new image data includes 22=4 sets of new image data that are separately forwarded to the driver circuit in respective four divisional time periods utilizing four lanes under Mobile Industry Processor Interface (MIPI) display serial interface specification provided for the timing controller.
In yet another aspect, the present disclosure provides a display apparatus including a timing controller having the processor described herein. Further, the display apparatus includes a driver circuit coupled to the timing controller to receive the four sets of new image data of N-bit generated by the timing controller based on image data of (N+2)-bit via four lanes in each time period. Additionally, the display apparatus includes a display panel driven by the driver circuit using the four sets of new image data to display image in the respective time period.
Optionally, the display panel is a LCD display panel. Optionally, the driver circuit is configured to drive the display panel using image data with grayscale levels up to 12-bit. The timing controller is configured with 4 lanes under Mobile Industry Processor Interface (MIPI) display serial interface specification to deliver data of 12-bit in four sets respectively in a time period. The timing controller includes the processor encoded with instruction for processing image data with enhanced grayscale levels up to 14-bit to generate four sets of new image data of 12-bit or lower and respectively sends the four sets of new image data to the driver circuit via the 4 lanes. The driver circuit thus drives the display panel to display image using the respective four sets of new image data of 12-bit or lower in the time period to achieve an image characteristics of grayscale levels up to 14-bit.
In another aspect, the present disclosure provides a non-transitory tangible computer-readable storage medium storing computer-readable instructions. In some embodiments, the computer-readable instructions being executable by a processor to cause the processor to perform receiving image data with a maximum grayscale level up to (M+N)-bit or M-bit higher than a regular maximum grayscale level of N-bit normally handled by the driver circuit of the display panel; dividing the image data of (M+N)-bit to a first set of data with low-order part M-bit data and a second set of data with high-order N-bit data of the (M+N)-bit data; reconstructing K sets of new image data with grayscale levels up to N-bit based on the first set of data and the second set of data; and forwarding the K sets of new image data to the driver circuit respectively in corresponding K divisional time periods defined by the timing controller of the display panel. Optionally, M is an integer equal to or greater than 2, N is an integer equal to or greater than 8, K is equal to 2M, and M is less than N.
The foregoing description of the embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. Therefore, the term “the invention”, “the present invention” or the like does not necessarily limit the claim scope to a specific embodiment, and the reference to exemplary embodiments of the invention does not imply a limitation on the invention, and no such limitation is to be inferred. The invention is limited only by the spirit and scope of the appended claims. Moreover, these claims may refer to use “first”, “second”, etc. following with noun or element. Such terms should be understood as a nomenclature and should not be construed as giving the limitation on the number of the elements modified by such nomenclature unless specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2018/085603 | 5/4/2018 | WO | 00 |
