Patent Application
20140295606
The present invention relates to the field of nano- and micro-electronics and concerns an improved method for forming a device provided with one or more gaps or cavities formed between a suspended element such as a membrane or beam for example and a substrate, the suspended element being held above the substrate via insulating posts.
With the invention it is possible to produce a device in which the height of the cavity or cavities is adjusted independently of the height of the insulating posts.
The invention also allows a device to be obtained having cavities of different heights.
It finds particular applications in the fabrication of Nano Electro Mechanical Systems and Micro Electro Mechanical Systems (NEMS/MEMS) and notably of electro-acoustic transducers e.g. Capacitive Micromachined Ultrasonic Transducers (cMUTS).
A MEMS transducer is generally formed of a fixed part provided with an electrode which can be formed in a semiconductor substrate 10, and of a membrane 40 forming a mobile electrode.
The membrane 40 rests on insulating posts 14a, 14b and together with the fixed part forms a cavity 50 in which it is intended to vibrate.
In said transducer, movements of the membrane 40 created by acoustic waves translate as electric signals, whilst electric signals applied to the mobile electrode and fixed electrode can allow actuation of the membrane 40.
The height H1 of the cavity 50 separating the substrate 10 from the membrane 40 is generally fixed by the height H2 of the insulating posts 14a, 14b. To enable good insulation and to reduce phenomena of parasitic capacitance, it is preferable to form insulating posts of good height H2.
At the same time, for reasons of efficient functioning and for some applications, it is also preferable to form cavities of low height H1. With low cavity height it is possible to cause actuation of the membrane 40 with low control voltages and to obtain a better signal when the device is in detection mode.
Document US 2009/0142872 describes a method for producing a cMUT transducer in which the insulating posts intended to support the membrane are formed by oxidizing the semiconductor substrate.
Said method can allow insulating posts to be formed which are partly buried in the substrate. It is therefore possible to form insulating posts of good height whilst limiting the height of the cavity. However, with said method the height of the cavity remains dependent upon the height of the insulating posts.
Document WO 2006/134580 A2 presents a method for forming a MEMS transducer in which the insulating posts are arranged at different depths of the outer surface of a substrate, a membrane being attached to some of these posts.
With said method the height of the cavities also remains dependent upon the height of the insulating posts.
The problem arises of finding a novel method which does not have the above-mentioned drawbacks, which allows a MEMS device to be obtained having insulating posts of good height whilst maintaining a cavity of low height.
The problem also arises of finding a novel method with which to obtain cavities of different heights.
The present invention provides a method for forming a device comprising one or more gaps such as cavities defined between a substrate in at least one given semiconductor material and a suspended element resting on the top of insulating posts projecting from the substrate, the method comprising steps of:
a) forming insulating posts either side of one or more regions of an upper surface of a substrate in at least one given semiconductor material;
b) modifying, via at least one etching and/or at least one addition of material, the distance between at least one given region from among the said regions of the said upper surface and the top of the insulating posts located either side of the said given region, the said insulating posts after step b) comprising at least one part located in the substrate and surrounded by the said given semiconductor material;
c) forming the suspended element on the top of said insulating posts.
At step b), the added material is semiconductive.
With said method, first the height is fixed of the insulating posts which are partly buried or inserted in the substrate, after which the height is fixed of one or more cavities formed between the suspended element and the substrate, by adding or removing material from the substrate after forming the posts.
It is therefore possible to obtain a device having cavities of low height e.g. between 10 nm and 5 μm, whilst maintaining a good thickness of the insulating posts e.g. between 0.1 μm and 10 μm.
At step b), the method may comprise at least one etching of said given region through a mask protecting at least one other region from among said regions of the upper surface of the substrate.
According to one variant, step b) may comprise epitaxial growth of semiconductor material on at least the said given region of the upper surface of the substrate.
The present invention also provides a method for forming a device comprising several gaps such as cavities defined between a substrate in at least one given semiconductor material and a suspended element resting on the top of insulating posts projecting from the substrate, the method comprising steps of:
a) forming insulating posts either side of one or more regions of an upper surface of a substrate in at least one given semiconductor material;
b) modifying, via at last one etching and/or addition of semiconductor material, the distance between at least one given region from among the said regions of said upper surface and the top of insulating posts positioned either side of said given region, a mask protecting at least one other region from among said regions of the upper surface of the substrate, the said insulating posts after step b) comprising at least one part positioned in the substrate and surrounded by said given semiconductor material;
c) forming the suspended element on the top of said insulating posts.
In this manner, cavities of different heights are formed between the substrate and the membrane.
Step c) to form the suspended element may comprise the transfer by direct bonding of the membrane onto the posts.
The membrane can subsequently be thinned after transfer.
The substrate may form a first electrode or comprise a first electrode e.g. an actuating and/or measuring electrode.
The suspended element e.g. a beam or membrane may form a second electrode or comprise a second electrode e.g. an actuating and/or measuring electrode.
According to one possible embodiment, the insulating posts may be formed in a given material which is not necessarily insulating, and of a top part in an insulating material allowing the substrate to be electrically insulated from the suspended element.
According to one possibility, the present invention may be applied to the production of a MEMS or NEMS.
The present invention may also be applied in particular to the fabrication of a cMUT transducer.
The said given region may be surrounded by one insulating post or several insulating posts contiguous with this region.
According to one particular embodiment, the said given region may be fully surrounded by one or more said insulating posts.
According to one possible embodiment, the said posts may be regularly distributed in an array.
The method at step a) may comprise steps of:
The height of the insulating posts is thus fixed in relation to the height of the semiconductor blocks.
According to a second possible embodiment, the forming of said insulating posts may comprise steps of:
According to another possibility, the forming of said insulating posts comprises the etching of an insulating layer resting on the substrate, so as to define insulating posts resting on the substrate.
The present invention will be better understood on reading the description of examples of embodiment given solely by way of indication and in no way limiting, with reference to the appended drawings in which:
A first example of a method according to the invention will now be described in connection with
The starting material of this method is a substrate 100 which may be in semiconductor material e.g. Si, and comprises regions 101a, 101b in the form of blocks created on a surface called the <<upper surface>> of the substrate 100.
The substrate 100 may be intended to form an electrode or to comprise a region intended to form an electrode, in particular if the device produced is a MEMS or NEMS, and more particularly a cMUT transducer.
These blocks may have been formed by etching the upper surface of the substrate 100, for example anisotropic etching through a mask.
Etching may be conducted for example using so-called <<dry>> etching by Reactive Ion Etch (RIE) or Deep Reactive Ion Etch (DRIE) , or using so-called <<wet>> etching via chemical route using reagents such as KOH or TMAH for example.
An insulating layer 102 is then formed on the substrate 100. This insulating layer 102 may be in SiO2 for example and formed by conformal deposition so that it reproduces the relief of the upper surface of the substrate 100.
The formed insulating layer 102 may therefore comprise regions 103a, 103b forming blocks reproducing the shape of the semiconductor blocks 101a, 101b on the surface of the substrate 100 (
A planarization step is subsequently conducted of the regions 103a, 103b of the insulating layer 102 e.g. by polishing of Chemical Mechanical Planarization type (CMP) or by etching. The surface of the insulating layer 102 is thus made planar or substantially planar. The thickness of the insulating layer 102 projecting beyond the top of the regions 101a, 101b may also be removed. In this manner insulating posts 104a, 104b, 104c are formed, derived from the insulating layer 102 and which may have a height H20 measured in a direction parallel to the vector {right arrow over (j)} of the orthogonal reference [O; ī; {right arrow over (j)}; {right arrow over (k)}] given in
The insulating posts 104a, 104b, 104c may therefore be formed so that they are buried in the substrate 100. The insulating posts 104a, 104b, 104c, may be entirely positioned within the substrate 100, the top of the insulating posts 104a, 104b, 104c and the upper surface of the substrate 100 lying at the same height. The sidewalls of the insulating posts 104a, 104b, 104c are therefore surrounded by the semiconductor material of the substrate 100.
A thickness of the upper surface of the substrate 100 is then removed, for example by plasma etching of the substrate.
This etching is performed so as to expose part of the sidewalls of the insulating posts 104a, 104b, 104c.
The lower part of the insulating posts 104a, 104b, 104c is thereby surrounded by the semiconductor material of the substrate 100 whilst an upper part of the posts is exposed and projects beyond the upper surface of the substrate 100 (
It is then possible to etch at least one given region 101b from among the said semiconductive regions 101a, 101b of the upper surface of the substrate 100 which are exposed. This etching is performed through a mask 120 protecting at least one other region 101a from among the said semiconductor regions 101a, 101b. A thickness of the given region 101b not protected by the mask 120 is therefore removed from the substrate 100 (
These removal steps can be performed using etching that is selective for the material of the insulating layer 102. This selective etching can be performed for example via plasma route of RIE or DRIE type when the regions 101a, 101b of the substrate 100 are in Si and the insulating layer 102 is in SiO2.
By means of this etching the distance is adjusted between the top of the insulating posts 104b, 104c and the given region(s) 101a and 101b. It is therefore possible to adjust the height of a cavity or portion of cavity intended to be subsequently formed between these given regions of the upper surface of the substrate and a membrane resting on the top of the insulating posts 104.
This step to adjust the height of the top of the posts 104a, 104b, 104c in relation to the upper surface of the substrate 100 can be conducted by means of several successive etchings if several cavity heights are desired.
As a variant, this adjustment can be obtained by selective epitaxy i.e. epitaxy on region 101b through a mask 120 protecting at least one other region 101a from among the said semiconductor regions 101a, 101b.
A suspended element can then be formed e.g. a membrane 140. The membrane 140 may be in monocrystalline silicon for example resting on the insulating posts 104a, 104b, 104c. The membrane 140 may be intended to form an electrode or comprises a region intended to form an electrode. This membrane 140 may be formed by transfer onto the posts 104a, 104b, 104c, for example by direct bonding onto the latter.
A step to thin the membrane 140 can then be carried out. This thinning may use one of more of the following techniques either alone or in combination: chemical etching and/or dry etching and/or grinding and/or chemical mechanical polishing (CMP).
Between this membrane 140 resting on the insulating posts 104a, 104b, 104c, and the substrate 100, one or more closed cavities 150a, 150b can be formed.
A first gap, in this example a first cavity 150a or portion of cavity 150a can be defined between a first region 101a of the substrate 100 and the membrane 140, and between the insulating posts 104a, 104b. This first cavity 150a or portion of cavity 150a may have a height H11 of between 10 nm and 5 μm for example, or in the order of 100 nm for example.
According to one possible embodiment, this first cavity 150a may optionally be closed so that it does not communicate with the outside or with another cavity.
A second gap, in this example a second cavity 150b or portion of cavity 150b defined between the given region 101b of the substrate 100 and the membrane 140 and between the insulating posts 104b, 104c may also be formed. This second cavity 150b or portion of cavity 150b may have a second height H12 different from the first height H11, and of between 50 nm and 5 μm for example, or in the order of several hundred nanometres for example. According to one possible embodiment, this second cavity 150b may optionally be closed so that it does not communicate with the outside or with another cavity (
A further example of the method of the invention is illustrated in
The starting material of this method is a substrate 100 coated with an insulating layer 102 in which separate posts 104a, 104b, 104c of height H20, are formed e.g. by etching. The insulating layer 102 may be in SiO2 for example or a <<low-k>> dielectric material such as SiOC (
Regions 101a, 101b of a surface of the substrate 100 called <<upper surface>> which are located between the insulating posts 104a, 104b, 104c are thus exposed.
An additional thickness of semiconductor material 201 is then formed on these regions 101a, 101b via selective epitaxial growth.
In this manner the distance between the top of the insulating posts 104a, 104b, 104c and the regions 101a, 101b of the upper surface of the substrate 100 can be adjusted (
Etching can subsequently be performed on at least one given region 101b from among the said semiconductor regions 101a, 101b. This etching can be conducted using dry etching of RIE or DRIE type for example through a mask 120 protecting at least one other region 101a from among the said semiconductor regions 101a, 101b.
It is therefore possible to adjust the height of one cavity 150b or portion of cavity which may be subsequently formed between the given region 101b of the substrate 100 and a membrane, and to make the height H12 of this cavity 150b higher than the height H11 of another portion of cavity or other cavity 150a subsequently formed between the region 101a of the substrate 100 and a membrane.
This membrane 140 can then be added in particular by bonding onto the insulating posts 104a, 104b, 104c in similar manner to the one previously described.
As a variant (
It is thus possible to adjust the height of a cavity 150b or portion of cavity subsequently formed between the given region 101b of the substrate 100 and a membrane 140, and to make the height H13 of this cavity 150b lower than the height H11 of another portion of cavity or other cavity 150a formed between the other region 101a of the substrate 100 and the membrane 140 (
A further example of a method according to the invention is illustrated in
The starting material in this example of method may be a semiconductor substrate 100 on which insulating regions 302a, 302b are formed. These insulating regions 302a, 302b may be in SiO2 for example respectively coated with oxidation masking regions 303a, 303b in Si3N4for example (
Anisotropic etching is then carried out e.g. of RIE or DRIE type on one surface of the substrate 100 called <<upper surface>> through the masking regions 303a, 303b stacked on the insulating regions 302a, 302b respectively.
This etching is performed so as to form trenches 305a, 305b, 305c in the substrates, blocks 301a, 301b of the substrate 100 being arranged either side of the trenches (
The depth of the trenches 305a, 305b, 305c is adjusted in relation to the depth it is desired to provide for insulating posts intended to be subsequently formed.
Thereafter, thermal oxidation is carried out of the semiconductor material of the substrate 100 to fill the trenches with insulating material.
The trenches filled with insulating material and oxidized regions of the substrate located in the continuation of these trenches form insulating posts 104a, 104b, 104c of which a bottom part is buried in the substrate 100 and located on one side of the upper surface of the substrate, the top part of the posts 104a, 104b, 104c projecting from the upper surface of the substrate 100. The thickness of the oxide created may be such that the upper surface of the created oxide lies flush or substantially flush with the level of the oxidizing masks 303a, 303b. By substantially flush is meant for example a difference in level of no more than 10 nm or 50 nm.
If the oxidization masking regions 303a, 303b are in Si3N4 for example, after oxidization (
The oxidation masking regions 303a, 303b may have been chosen to have an initial thickness that is sufficiently narrow e.g. in the order of 100 nm, so that they can be converted by oxidization, and in particular so that they can be converted to SiOxNy if these regions were initially in Si3N4.
Planarization e.g. using chemical mechanical polishing (CMP) is then carried out to remove excess thicknesses of insulating material. After this removal, a substrate 100 is obtained which, on its upper surface, comprises semiconductor regions 101a, 101b, and insulating posts 104a, 104b, 104c arranged either side of these semiconductor regions 101a, 101b, and arranged so as to have a bottom part buried in the substrate 100 and is therefore surrounded by the semiconductor material of the substrate 100 (
It is then possible to implement a method such as previously described in connection with
In
In
With said arrangement it is possible to form a closed cavity delimited between the insulating posts 104a, 104b, 104c, the substrate 100 and the membrane 140.
In
With said arrangement it is possible to form open cavities.
In
In
| Number | Date | Country | Kind |
|---|---|---|---|
| 1160208 | Nov 2011 | FR | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/EP2012/072156 | 11/8/2012 | WO | 00 | 5/1/2014 |
