The present invention relates to the manufacture of via contacts through semiconductor substrates. Electrically conductive connections between the top side and the bottom side of a semiconductor substrate are used for the vertical integration of semiconductor components.
For the connection of multiple semiconductor components, semiconductor chips can be arranged one next to the other and can be connected in an electrically conductive way to each other by wires, or multiple semiconductor chips can be arranged stacked vertically one above the other and can be connected to each other by electrical connection contacts on the top sides and bottom sides. When the semiconductor chips are stacked, electrically conductive connections must be established through the substrate from the top side of each chip to the bottom side. For this purpose, holes are typically etched into the substrate, wherein these holes are then filled with an electrically conductive material, typically a metal. If the electrical conductor is established so that it does not reach up to the back side of the substrate, then the substrate is thinned from the back side by grinding until the conductive material of the contact-hole filling is exposed and the via contact is created. On the surfaces of the substrate, metal layers can be deposited as connection metalization and can be structured corresponding to the provided connections. When the chips are stacked, the connection contact faces allocated to each other are arranged one above the other and are connected to each other permanently in an electrically conductive way, for example, by means of a solder. (J. Vardaman, “3-D Through-Silicon Vias Become a Reality,” Semiconductor International, Jun. 1, 2007)
Typical approaches create via contacts with diameters of 10 μm to 50 μm, wherein the contact holes are filled with copper (T. Rowbotham et al., “Back side exposure of variable size through silicon vias,” J. Vac. Sci. Techn. B24(5), 2006) or polycrystalline silicon (E. M. Chow et al., “Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates,” J. of Micromechanical Systems, Vol. 11, No. 6, 2002; J. H. Wu et al., “Through-Wafer Interconnect in Silicon for RFICs,” IEEE Trans. on El. Dev. 51, No. 11, 2004) or covered with organic material (N. Lietaer et al., “Development of cost-effective high-density through-wafer interconnects for 3-D microsystems,” J. of Micromechanics and Microengineering 16, S29-S34, 2006).
Large-dimensioned via contacts in semiconductor wafers are created, for example, through the etching of large cutouts with angled side walls, for example, under the use of KOH. A metal layer deposited in the cutout is exposed from the opposite top side of the wafer and is provided there with a contact. Conventional methods are described in US 2005/156330, US 2005/090096, U.S. Pat. No. 6,323,546, U.S. Pat. No. 6,483,147, U.S. Pat. No. 6,159,833, JP 2001 116768, U.S. Pat. No. 6,352,923, U.S. Pat. No. 6,252,300, U.S. Pat. No. 6,110,825, U.S. Pat. No. 5,511,428, and CA 1 057 411.
It is an object of the present invention to disclose improved methods and structures for the economical manufacture of via contacts through semiconductor substrates that can be applied, in particular, also for thicker wafers of typically greater than 100 μm thickness. An associated manufacturing method is to be carried out with processing steps of a standard CMOS process.
This object is achieved with the method for the manufacture of a semiconductor component with the features. of claim 1 or with the semiconductor component with the features of claim 12, respectively. Embodiments emerge from the dependent claims.
In the case of the via contacts according to the invention, it is provided to coat only the side walls and the base of a contact hole with electrically conductive material. In the case of preferred embodiments, a dielectric layer, a metallization, and a passivation are deposited. With the exception of the contact hole etching, the processing steps used belong to standard CMOS processes. For example, via contacts with typical diameters of 100 μm in a substrate with a typical thickness of approximately 250 μm can be realized.
Below is a more detailed description of examples of the semiconductor component and the manufacturing method with reference to the accompanying figures.
A preferred embodiment of the semiconductor component will now be described with reference to a preferred manufacturing method. In the case of this embodiment, it is assumed that the semiconductor component comprises a CMOS circuit. The CMOS circuit is integrated in a substrate that has the structure of a SOI substrate. The semiconductor material of the substrate is preferably silicon. The CMOS components are integrated in a thin, monocrystalline silicon layer, conventionally designated as a body silicon layer, which is arranged on an insulation layer. A via contact to the back side of the substrate is to be created from the top side of the body silicon layer.
In the cross section of
The substrate 1 has an insulation layer 2 that separates the substrate 1 into a top-side semiconductor layer 3 and a portion conventionally designated as bulk. In the case of a silicon substrate, the semiconductor layer 3 is designated as the body silicon layer. Within the insulation layer 2, according to the invention, a connection pad 7 made from an electrically conductive material, preferably a metal, is arranged. The connection pad 7 can be limited laterally, as shown in
The shown arrangement can be manufactured, for example, by a known wafer bonding process. In the case of this process, two semiconductor substrates or wafers are used. The top side of the one substrate is provided with the insulation layer 2. Then the insulation layer 2 is permanently mounted on a top side of the other substrate. In this way, the layer sequence shown in the cross section in
A mask 8 is applied and structured on the top side of the component. This mask is, for example, a photoresist mask that is formed relatively thick. By means of the mask 8, the opening 9 is etched into the layers of the liner 6 and the intermetal dielectric 4 present between the metal planes 5.
The dielectric layer 10 is removed on the topside, that is, on the liner 6, and on the base of the opening 9, as is shown in cross section in
The metallization 11 can then be contacted on the top side by the deposition of a top-side connection metallization designated in the following as top metal. Therefore, any metal typically used for conductor tracks is suitable, in particular, for example, aluminum.
For embodiments with multiple-layer passivation 13, optionally the properties of the relevant materials important for tempering steps, for example, the coefficients of thermal expansion, are taken into account in the sequence of the entire process. Otherwise, it could happen that cracks appear in the passivation 13 or that the passivation 13 peels from the bottom layer, which can occur on the metallization 11 mainly in the area of the side wall of the opening 9. That must be avoided when tempering steps are performed in which the component is heated to a temperature of typically 400° C. to 500° C., for example, in order to saturate so-called “dangling bonds” of the silicon in the area of integrated components, which is performed under a forming-gas atmosphere (for example, under a mixture of hydrogen and nitrogen) and is designated as “forming gas alloy.” For such embodiments, the tempering step has preferably already been performed before the passivation is deposited or, in any case, before an additional layer made from different material is deposited on a layer of the passivation 13, that is, in the described example, the nitride layer on an oxide layer, or an additional layer created with a different method (for example, SACVD instead of PECVD) is deposited. Thus, the tempering step is preferably performed in embodiments with layers of different thermal properties before the passivation 13 is deposited or has been completely deposited, so that, in each case, it is deposited before the last layer of the passivation 13 is created.
Starting from the structure shown in cross section in
In comparison with a standard CMOS process, no additional masks are required for the described method, with the exception of the etching step for the production of the opening 9. The method is therefore suitable especially for the production of CMOS components with via contacts through the substrate. The structure of the component is characterized by the conductive connection of the via contact that does not fill the opening 9, but instead is present only on the side walls, as well as by the buried connection pad 7. This structure has the special advantages that the ohmic resistance of the via contact is especially low due to the comparatively very large surface area of the side wall of the opening used for this purpose and that the passivation 13 can be deposited by means of a standard PECVD process and optionally a SACVD process.
Number | Date | Country | Kind |
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10 2008 033 395.6 | Jul 2008 | DE | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/EP2009/058001 | 6/25/2009 | WO | 00 | 4/14/2011 |