Claims
- 1. A method for producing a MOS transistor, the method comprising:
- a. forming two trenches at a surface of a first substrate;
- b. forming a first dielectric layer into said two trenches;
- c. placing a second substrate onto said surface of said first substrate;
- d. delaminating a layer from said first substrate, said layer including said two trenches and a portion of said first substrate;
- e. bonding said layer to said second substrate; and
- f. forming, in said portion of said first substrate, first and second active regions.
- 2. The method of claim 1 further including forming a gate overlaying a space between said two trenches.
- 3. The method of claim 2 wherein forming, a gate overlaying a space between said first and second active regions includes aligning said gate with said space.
- 4. The method of claim 1 wherein delaminating a layer from the first substrate includes creating a stress surface into the first substrate said stress surface defining said portion of said first substrate.
- 5. The method of claim 4 wherein creating a stress surface includes implanting hydrogen ions into said first substrate.
- 6. The method of claim 4 wherein delaminating a layer from the first substrate further includes heating said first substrate and said second substrate to a temperature in a first approximate range of 400.degree. to 600.degree. C.
- 7. The method of claim 4 wherein said portion of said first substrate has a thickness, measured from a surface of the two trenches to the stress surface in the approximate range of 0.05 .mu.m-0.2 .mu.m.
- 8. The method of claim 1 wherein bonding said layer to said second substrate includes heating the first and second substrates to a temperature in a second approximate range of 800.degree. to 1000.degree. C.
- 9. The method of claim 1 further including polishing said stress surface.
- 10. The method of claim 1 wherein forming, in said portion of said first substrate, first and second active regions includes aligning said first and second active regions with said two trenches.
- 11. The method of claim 1 wherein said two trenches have a depth in the approximate range of 0.1-0.3 .mu.m.
- 12. A method for producing a transistor, the method comprising
- a. forming a trench at a surface of a first substrate as viewed from a top side, said trench having a surface spaced apart from said surface of said first substrate;
- b. depositing oxide onto said trench;
- c. placing a second substrate to down onto said surface of said first substrate;
- d. delaminating a layer from said first substrate, said layer including said trench and a portion of said first substrate;
- e. bonding said layer to said second substrate forming a composite structure; and
- f. forming, as viewed from the flipped side of the composite structure wherein the said layer is on top in said portion of said first substrate, an active region overlaying said surface of said oxide-filled trench.
- 13. The method of claim 12 wherein creating a stress surface includes implanting hydrogen ions into said first substrate.
- 14. The method of claim 13 wherein creating a stress surface includes implanting Hydrogen ions into said first substrate.
- 15. The method of claim 12 wherein delaminating a layer from said first substrate further includes heating said first substrate and said second substrate to a temperature in a first approximate range of 400.degree. to 600.degree. C.
- 16. The method of claim 12 wherein bonding said layer to said second substrate includes heating the first and second substrates to a temperature in a second approximate range of 800.degree. to 1000.degree. C.
- 17. The method of claim 12 wherein forming in said portion of said first substrate an active region includes aligning said active region with said oxidefilled trench.
- 18. A method of forming a transistor, the method comprising
- a. forming a first trench in a semiconductor substrate;
- b. filling the first trench with a dielectric material;
- c. placing a second substrate onto the semiconductor substrate;
- d. delaminating a portion of the semiconductor substrate, the portion including the first trench and adjacent semiconductor materials; and
- e. forming an active region in said adjacent semiconductor material.
- 19. The method of claim 18 further including forming a trench on a surface of said semiconductor surface.
Parent Case Info
This is a divisional application of copending application Ser. No. 08/884,921, filed Jun. 30, 1997 that issued as U.S. Pat. No. 5,949,108. I hereby claim the benefit under Title 35, U.S. Code, Section 120 of the U.S. Pat. No. 5,949,108, issued on Sep. 7, 1999.
US Referenced Citations (10)
Foreign Referenced Citations (2)
Number |
Date |
Country |
5-75123 |
Mar 1993 |
JPX |
5-167063 |
Jul 1993 |
JPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
884921 |
Jun 1997 |
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