Patent Grant
9064823
In semiconductor manufacturing, semiconductor wafers often undergo many processing steps or stages before a completed die is formed. For example, thermal processing is often performed on wafers for various purposes, such as Shallow Trench Isolation (STI), repairing film defects, dopant activation from ion implantations, and film property transformation, among others.
Bulk Micro Defects (BMDs) may be further induced by thermal processing, as proven useful in semiconductor processing for metal contamination gathering effects. Although BMDs may provide the advantageous metal gathering effect, the thermal processing associated with the formation of the BMDs also has a tendency to reduce wafer strength, which can lead to undesirable wafer distortion (warping), substrate lattice dislocation, and/or broken wafers which lead to failures of the wafer and lower yields of final products.
Conventional methods for maintaining wafer strength have been primarily limited to controlling an overall oxygen concentration and crystalline defect densities across an entire semiconductor ingot during the ingot preparation process.
The following presents an overview of the disclosure in order to provide a basic understanding of one or more aspects of the disclosure. This is not an extensive overview of the disclosure, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.
In one embodiment, the present disclosure relates to a method for qualifying a semiconductor wafer for subsequent processing, such as thermal processing. The method comprises defining a plurality of locations about a periphery of the semiconductor wafer and measuring one or more properties of the semiconductor wafer at each of the plurality of locations. The one or more properties, for example, comprise an oxygen concentration and a density of bulk micro defects present at each of the plurality of locations about the periphery of the semiconductor wafer. In several examples, a statistical profile associated with the periphery of the semiconductor wafer is determined, based on the one or more properties measured at the plurality of locations. Subsequently, the semiconductor wafer is permitted to undergo thermal treatment when the statistical profile falls within a predetermined range, and the semiconductor wafer is rejected or prevented from such subsequent thermal processing when the statistical profile deviates from the predetermined range.
According to one or more examples, the statistical profile associated with the periphery of the semiconductor wafer is determined by dividing a difference between a maximum and a minimum of the respective one or more properties measured at the plurality of locations by a statistical mean of the respective one or more properties at the plurality of locations. In one example the predetermined range in which a semiconductor wafer is permitted to undergo subsequent thermal processing comprises a statistical profile of bulk micro defects ranging between zero and one.
The present disclosure provides a method for qualifying a semiconductor wafer for subsequent processing, such as thermal processing. Accordingly, the description is made with reference to the drawings, in which like reference numerals are generally utilized to refer to like elements throughout, and wherein the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to facilitate understanding. It may be evident, however, to one skilled in the art, that one or more aspects described herein may be practiced with a lesser degree of these specific details. In other instances, known structures and devices are shown in block diagram form to facilitate understanding.
In semiconductor manufacturing, bulk micro defects (BMDs) have been evidenced in semiconductor wafers and/or semiconductor ingots, and have been advantageously utilized to provide metal contamination gathering effects. Although BMDs may provide the advantageous metal gathering effect, the thermal processing associated with the formation of the BMDs also has a tendency to reduce wafer strength, which can lead to undesirable wafer distortion (warping), substrate lattice dislocation, and/or broken wafers which lead to failures of the wafer and lower yields of final products. In some instances, the semiconductor wafer comprises Czochralski (CZ) and float-zone (FZ) crystals formed therein, which can further reduce wafer strength due to additional crystal defects imposed in the wafer.
Heretofore, examination of BMDs in a semiconductor workpiece have not taken into consideration the distribution of BMDs in an edge or periphery of the semiconductor wafer. The present disclosure finds a new appreciation that the BMD distribution in the wafer edge affects stresses in the wafer during subsequent thermal processing. Accordingly, an analysis of the edge of the semiconductor wafer can advantageously predict subsequent failures and maintain adequate metal ion gathering abilities of the wafer. Thus, the analysis of the present disclosure can be utilized to qualify wafers for subsequent processing, wherein losses due to breakage and/or performance can be minimized.
Referring now to
Referring now to
In act 204, one or more properties of the semiconductor wafer are measured at each of the plurality of locations. The one or more properties, for example, comprise one or more of an oxygen concentration and a density of bulk micro defects present at each of the plurality of locations. Measuring the one or more properties of the semiconductor wafer, for example, comprises analyzing the semiconductor wafer 105 of
In act 206, a statistical profile associated with the periphery of the semiconductor wafer is determined, wherein the statistical profile is based on the one or more properties measured at the plurality of locations. The statistical profile determined in act 206 for example, comprises dividing a difference between a maximum and a minimum of the respective one or more properties measured at the plurality of locations by a statistical mean of the respective one or more properties at the plurality of locations. For example, a minimum measured density of BMDs is subtracted from a maximum measured density of BMDs from the measurement of act 204, and the difference is divided by a statistical mean of the plurality of measured densities of BMDs, thus yielding the statistical profile associated with the periphery of the semiconductor wafer.
In act 208, a determination is made as to whether the statistical profile garnered in act 206 is acceptable. For example, if the statistical profile falls within a predetermined range, the semiconductor wafer is sent for subsequent processing, such as thermal treatment or other processing in act 210. If the statistical profile deviates or does not fall within the predetermined range, the semiconductor wafer is rejected from subsequent processing in act 212, thereby mitigating potential defects such as warpage, breakage, or other wafer distortion. The predetermined range, for example, comprises a statistical profile for BDMs ranging between zero and one. In other examples, the one or more properties measured in act 204 comprise the oxygen concentration. As such, the predetermined range of the statistical profile, for example, can comprise an oxygen concentration ranging between approximately 9.5 parts per million atoms and approximately 11.5 parts per million atoms.
In accordance with another aspect, the aforementioned methodology may be implemented using computer program code in one or more general purpose computer or processor based system. As illustrated in
The bus 310 may be one or more of any type of several bus architectures including a memory bus or memory controller, a peripheral bus, or video bus. The CPU 304 may include any type of electronic data processor, and the memory 306 may include any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM).
The mass storage device 308 may include any type of storage device configured to store data, programs, and other information and to make the data, programs, and other information accessible via the bus 310. The mass storage device 308 may include, for example, one or more of a hard disk drive, a magnetic disk drive, or an optical disk drive.
The video adapter 312 and the I/O interface 314 provide interfaces to couple external input and output devices to the processing unit 302. Examples of input and output devices include the display 318 coupled to the video adapter 312 and the I/O device 320, such as a mouse, keyboard, printer, and the like, coupled to the I/O interface 314. Other devices may be coupled to the processing unit 302, and additional or fewer interface cards may be utilized. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. The processing unit 302 also may include a network interface 316 that may be a wired link to a local area network (LAN) or a wide area network (WAN) 322 and/or a wireless link.
It should be noted that the processor based system 300 may include other components. For example, the processor based system 300 may include power supplies, cables, a motherboard, removable storage media, cases, and the like. These other components, although not shown, are considered part of the processor based system 300.
Embodiments of the present disclosure may be implemented on the processor based system 300, such as by program code executed by the CPU 304. Various methods according to the above-described embodiments may be implemented by program code. Accordingly, explicit discussion herein is omitted.
Further, it should be noted that the modules and devices in
Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
While the method(s) provided herein is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.
It will be appreciated that while reference is made throughout this document to exemplary structures in discussing aspects of methodologies described herein, that those methodologies are not to be limited by the corresponding structures presented. Rather, the methodologies (and structures) are to be considered independent of one another and able to stand alone and be practiced without regard to any of the particular aspects depicted in the Figs.
Also, equivalent alterations and/or modifications may occur to those skilled in the art based upon a reading and/or understanding of the specification and annexed drawings. The disclosure herein includes all such modifications and alterations and is generally not intended to be limited thereby. In addition, while a particular feature or aspect may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features and/or aspects of other implementations as may be desired. Furthermore, to the extent that the terms “includes”, “having”, “has”, “with”, and/or variants thereof are used herein, such terms are intended to be inclusive in meaning—like “comprising.” Also, “exemplary” is merely meant to mean an example, rather than the best. It is also to be appreciated that features, layers and/or elements depicted herein are illustrated with particular dimensions and/or orientations relative to one another for purposes of simplicity and ease of understanding, and that the actual dimensions and/or orientations may differ substantially from that illustrated herein.
This application is a Non-Provisional patent application claiming priority to U.S. Provisional Patent Application Ser. No. 61/778,774 filed Mar. 13, 2013, entitled “Improved Wafer Strength by Control of Uniformity of Edge Bulk Micro Defects” in the name of I-Che Huang, et al., and is hereby incorporated by reference.
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