METHOD FOR READING MEMORY DEVICE AND MEMORY DEVICE

Abstract

A method for reading a memory device is provided. The memory device includes a first word line, a second word line, and memory cells. The memory cells include first memory cells coupled to the first word line and second memory cells coupled to the second word line. Each memory cell is configured to storing M bits data, and M is a positive integer greater than or equal to 2. At least one first voltage is applied to the first word line. After applying the at least one first voltage to the first word line, a read operation of reading a first level of 2M levels of the second memory cells is performed, including performing a first and a second read operations based on a first and a second conditions respectively. The first condition is different from the second condition, and the first condition and the second condition comprise a voltage or a time.

Description

TECHNICAL FIELD

Implementations of the present disclosure relate to the field of semiconductor, and particularly to a method for reading a memory device and a memory device.

BACKGROUND

In a three-dimensional NAND flash memory (3D NAND Flash), one-time programming is typically used for trinary-level cell (TLC) (i.e., 3-bit data being stored per memory cell) products. The state of memory cells of a TLC product in a reading process is different from that in a programming verification process. WLn+1 (i.e., the (n+1)^th word line) is not programmed in the programming verification, while in most cases, the WLn+1 is programmed in the reading process.

However, in the NAND flash memory according to the related art, writing the WLn+1 would cause deviation of a threshold voltage of the memory cell on the WLn (i.e., the n^th word line), and thus cause an error in data reading.

SUMMARY

The present disclosure provides a method for reading a memory device, where the memory device includes a plurality of word lines and a plurality of multi-bit memory cells connected to the plurality of word lines, and each of the multi-bit memory cells is configured such that a stored value of the multi-bit memory cell is read through multi-level preset read voltages, and the method including: reading a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell by using at least one sampling voltage, and determining at least one offset flag, each representing a size of a respective one of at least one read offset according to a sampling read value of each of the at least one sampling voltage; wherein the at least one sampling voltage is at least one of the multi-level preset read voltages; wherein the at least one sampling voltage comprises N sampling voltages, each of the multi-level preset read voltages corresponds to N+1 read offsets, and N is a positive integer greater than or equal to 2; and reading the to-be-read multi-bit memory cell, according to the multi-level preset read voltages and the at least one read offset of each of the multi-level preset read voltages, each corresponding to a respective one of the at least one offset flag.

In another aspect, the present disclosure further provides a memory device including a memory cell array and a peripheral circuit coupled to the memory cell array; where the memory cell array includes a plurality of word lines and a plurality of multi-bit memory cells connected to the plurality of word lines; the peripheral circuit is configured to read stored values of the multi-bit memory cells through multi-level preset read voltages, and the peripheral circuit is configured to read a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell by using at least one sampling voltage, and determine at least one offset flag, each representing a size of a respective one of at least one read offset according to a sampling read value of each of the at least one sampling voltage; and read the to-be-read multi-bit memory cell, according to the multi-level preset read voltages and the at least one read offset of each of the multi-level preset read voltages, each corresponding to respective one of the at least one offset flag; the at least one sampling voltage is at least one of the multi-level preset read voltages; wherein the at least one sampling voltage comprises N sampling voltages, each of the multi-level preset read voltages corresponds to N+1 read offsets, and N is a positive integer greater than or equal to 2.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the present disclosure, the accompanying drawings used in the description of the implementations according to the present disclosure are briefly described below. The accompanying drawings in the following description are merely some implementations of the present disclosure, and other figures may be obtained from the figures without creative effort by those skilled in the art.

FIG. 1 is a flowchart of a method for reading a memory device according to an implementation of the present disclosure.

FIG. 2 is a further flowchart of a method for reading a memory device according to an implementation of the present disclosure.

FIG. 3 is a schematic structural diagram of a voltage compensation device according to an implementation of the present disclosure.

FIG. 4 is another schematic structural diagram of a voltage compensation device according to an implementation of the present disclosure.

DETAILED DESCRIPTION

The technical solutions in the implementations of the present disclosure is described below in conjunction with the accompanying drawings of the implementations of the present disclosure. The described implementations are only a part of the implementations of the present disclosure, rather than all of the implementations. Based on the implementations of the disclosure, all other implementations obtained by those skilled in the art without creative effort are within the scope of the disclosure.

The present disclosure is directed to a technical problem in the related art that when an adjacent word line of a to-be-read multi-bit memory cell of a memory device is being programmed, a shift in the threshold voltage of the to-be-read multi-bit memory cell is caused, and implementations according to the present disclosure are proposed to solve the problem.

Referring to FIG. 1, which is a flowchart of a method for reading a memory device according to an implementation of the present disclosure. The memory device includes a plurality of word lines and a plurality of multi-bit memory cells connected to the plurality of word lines, and each of the multi-bit memory cells is configured such that a stored value of the multi-bit memory cell is read through multi-level preset read voltages. The method for reading the memory device includes the following steps.

In a defining step S101, at least one read offset is defined for each of the multi-level preset read voltages.

In an offset setting step S102, at least one of preset read voltages is selected as at least one sampling voltage from the multi-level preset read voltages, a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell is read, and at least one offset flag, each representing a size of a respective one of the at least one read offset, is set according to a sampling reading value of a respective one of the at least one sampling voltage.

In a reading step S103, the to-be-read multi-bit memory cell is read according to the multi-level preset read voltages and the at least one read offset of each of the multi-level preset read voltages, each corresponding to a respective one of the at least one offset flag.

It should be noted that each of the multi-bit memory cells can store multi-bit data; the multi-bit memory cells may include but not limited to a multi-level cell (MLC), a trinary-level cell (TLC), a quad-level cell (QLC), and the like. In the implementations, the TLC is described. The TLC may be programmed in one of eight-level threshold voltages, and for each level threshold voltage of the eight-level threshold voltages, the TLC has a respective memory state, so that the trinary-level cell can store eight data. By applying a preset read voltage to the TLC, it can be determined which memory state the trinary-level cell is in, and then the stored value can be read out.

Further, each of the multi-bit memory cells has multi-level preset read voltages to read out the stored value of the multi-bit memory cell in different memory states. In the defining step S101, at least one read offset may be set for each of the multi-level preset read voltages, and at least one read offset may be set, so that the preset read voltage can be compensated when the multi-bit memory cell is subsequently read, thereby solving the problem of the shift of the threshold voltage of the multi-bit memory cell.

Referring to FIG. 2, which is a further flowchart of a method for reading a memory device according to an implementation of the present disclosure. Each of the plurality of multi-bit memory cells may be configured to be programmed with one of multi-level threshold voltages. When the at least one sampling voltage includes N sampling voltages, the multi-bit memory cell may fall into one of N+1 sampling reading value partitions due to differences of the multi-level threshold voltages, and each of sampling reading value partitions corresponds to a respective offset flag. As shown in FIG. 2, the offset setting step S102 may further include the following steps.

In a sampling reading value obtaining step S1021, a reading value of the multi-bit memory cell on the adjacent word line of the to-be-read multi-bit memory cell is obtained by using the N sampling voltages.

In a sampling reading value partitioning step S1022, the multi-bit memory cell on the adjacent word line of the to-be-read multi-bit memory cell is classified into one of the N+1 sampling reading value partitions according to the reading value.

In an offset flag obtaining step S1023, an offset flag corresponding to the classified sampling reading value partition is obtained.

It should be noted that when the at least one sampling voltage includes one sampling voltage, there may be two sampling reading value partitions corresponding to the sampling voltage, and each of the sampling reading value partitions corresponds to a respective offset flag. Since the offset flag is represented by log₂ (N+1) bits, only one bit is required to represent the offset flag at this time, and the offset flag is stored in a program block latch of the memory device and has a value of 0 and a value of 1. When the at least one sampling voltage includes three sampling voltages, there may be four sampling reading value partitions corresponding to the sampling voltages, and two bits are required to represent the offset flag at this time, which has a value of 00, a value of 01, a value of 10, and a value of 11.

Further, taking one sampling voltage as an example, for example, if a sampling reading voltage R4 is taken, sampling reading values of memory cells whose threshold voltages are E, P1, P2, and P3 may be set to be 0, and sampling reading values of memory cells whose threshold voltages are P4, P5, P6, and P7 may be set to be 1. Taking three sampling voltages as an example, for example, if three sampling reading voltages R1, R4, and R7 are taken, sampling reading values of memory cells whose threshold voltages are E may be set to 00, sampling reading values of memory cells whose threshold voltages are P1, P2, and P3 may be set to be 01, sampling reading value of memory cells whose threshold value voltages are P4, P5, and P7 may be set to be 10, and sampling reading value of memory cells whose threshold value voltages are P7 may be set to be 10.

Continuing to refer to FIG. 2, the reading step S103 may include the following steps.

In determining step S1031, a current read offset of the preset read voltage of the level corresponding to the offset flag is determined.

In performing step S1032, reading of the to-be-read multi-bit memory cell is performed with a voltage that is a sum of the level preset read voltage and the current read offset.

It should be noted that when the at least one sampling voltage includes N sampling voltages, each of the multi-level preset read voltages has (N+1)-level read offsets, and a first-level read offset of the N+1 read offsets is 0. For example, when the at least one sampling voltage includes one sampling voltage, two-level read offsets may be set, and a first-level read offset of the two-level read offsets is 0. When the at least one sampling voltage includes three sampling voltages, fourth-level read offsets may be set, and a first-level read offset of the fourth-level read offsets is 0. For example, for the first-level preset read voltage, there may be three types of offsets: Offset1_R1, Offset2_R1, Offset3_R1; for the second-level preset read voltage, there may be three types of offsets: Offset1_R2, Offset2_R2, Offset3_R2, . . . , until for the seventh-level preset read voltage, there may be three types of offsets: Offset1_R7, Offset2_R7, Offset3_R7. Further, the read offsets include one of a voltage offset value and a voltage offset time.

In some implementations, the adjacent word line may be a word line immediately subsequent to a word line on which the to-be-read multi-bit memory cell is located. Further, according to the method for reading the memory device, the edge summation (ESUM) can be improved to 120 mV.

In an exemplary implementation, the multi-bit memory cells may be TLCs, and the fourth-level preset read voltage of the eight-level preset read voltages may be selected as the sampling voltage. In this case, there may be two sampling reading value partitions corresponding to the sampling voltage. That is, the zeroth-level to the third-level preset read voltages are in the first sampling reading value partition, the fourth-level to seventh-level preset read voltages are in the second sampling reading value partition, and each level of the preset read voltages may have two-level read offsets, where the first-level read offset may be 0. In the implementation, the adjacent word line is WLn+1, and the current word line is WLn. When WLn+1 is in the first sampling reading value partition, the read offset of WLn is 0; and when WLn+1 is in the second sampling reading value partition, the read offset of WLn is as the following.

WLn level	1	2	3	4	5	6	7
Read offset	80	70	70	60	60	60	50

The present disclosure provides a method for reading a memory device. The memory device includes a plurality of word lines and a plurality of multi-bit memory cells connected to the plurality of word lines, and each of the multi-bit memory cells is configured such that a stored value of the multi-bit memory cell is read through multi-level preset read voltages. The method includes: defining at least one read offset for each of the multi-level preset read voltages respectively, selecting at least one of preset read voltage of the multi-level preset read voltage as the at least one sampling voltage, reading a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell, and setting at least one offset flag, each representing a size of a respective one of the at least one read offset according to a sampling reading value of a respective one of the at least one sampling voltage; and then, the method further includes reading the to-be-read multi-bit memory cell according to the multi-level preset read voltages and the at least one read offset of each of the multi-level preset read voltages, each corresponding to a respective one of the at least one offset flag. Thus, the preset read voltages of the to-be-read multi-bit memory cell can be compensated, thereby effectively solving the problem of shift of threshold voltages of the to-be-read multi-bit memory cell that is caused when the adjacent word line of the to-be-read multi-bit memory cell of the memory device is being programmed.

Referring to FIG. 3, which is a schematic structural diagram of a voltage compensation device according to an implementation of the present disclosure. The voltage compensation device is applied to a memory device including a plurality of word lines and a plurality of multi-bit memory cells connected to the plurality of word lines, and each of the multi-bit memory cells is configured such that a stored value of the multi-bit memory cell is read through multi-level preset read voltages.

In practical applications, the memory device may include a memory cell array and a peripheral circuit. The memory cell array may include a plurality of memory blocks, each of the memory blocks includes a plurality of memory pages, and each of the memory pages includes a plurality of memory cells.

The peripheral circuit may include any suitable digital, analog, and/or mixed-signal circuit configured to facilitate various operations of the memory device such as reading operations, writing operations, erasing operations, and the like. For example, the peripheral circuit may include control logic (e.g., a control circuit or a controller), a data buffer, a decoder, a driver, a reading/writing circuit, and the like. When the control logic receives a reading/writing operation command and address data, the decoder may apply, based on a decoded address, a corresponding voltage from the driver to a corresponding bit line and word line under the control of the control logic, to implement data reading and writing and perform data exchange with external entities through the data buffer.

The voltage compensation device provided in the implementation may include a definition module 10, an offset setting module 20, and a reading module 30.

(1) Definition Module 10

The definition module 10 is configured to perform the definition step S101; that is, the definition module 10 is configured to define at least one read offset for each of the multi-level preset read voltages respectively.

(2) Offset Setting Module 20

The offset setting module 20 is configured to perform an offset setting step S102; that is, the offset setting module 20 is configured to select at least one of the multi-level preset read voltages as at least one sampling voltage, read a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell, and set at least one offset flag, each representing a size of a respective one of the at least one read offset according to a sampling reading value of a respective one of the at least one sampling voltage.

It should be noted that each of the multi-bit memory cells can store multi-bit data; the multi-bit memory cells may include but are not limited to a multi-level cell (MLC), a trinary-level cell (TLC), a quad-level cell (QLC), and the like. In the implementations, the TLC is described. The TLC may be programmed in one of eight-level threshold voltages, and for each level threshold voltage of the eight-level threshold voltages, the TLC has a respective memory state, so that the trinary-level cell can store eight data. By applying a preset read voltage to the TLC, it can be determined which memory state the trinary-level cell is in, and then the stored value can be read out.

Further, each of the multi-bit memory cells has multi-level preset read voltages to read out the stored value of the multi-bit memory cell in different memory states. In the defining step S101, at least one read offset may be set for each of the multi-level preset read voltages, and at least one read offset may be set, so that the preset read voltage can be compensated when the multi-bit memory cell is subsequently read, thereby solving the problem of the shift of the threshold voltage of the multi-bit memory cell.

Furthermore, referring to FIG. 4, which is another schematic structural diagram of a voltage compensation device according to an implementation of the present disclosure. Each of the plurality of multi-bit memory cells may be configured to be programmed in one of multi-level threshold voltages. When the at least one sampling voltage includes N sampling voltages, the multi-bit memory cell may fall into one of N+1 sampling reading value partitions due to differences of the multi-level threshold voltages, and each of sampling reading value partitions may correspond to a respective one of the offset flags. The offset setting module 20 may further include a sampling reading value obtaining unit 21, a reading value partitioning unit 22, and an offset flag obtaining unit 23.

The sampling reading value obtaining unit 21 may be configured to obtain, by using the N sampling voltages, a reading value of the multi-bit memory cell on the adjacent word line of the to-be-read multi-bit memory cell.

The reading value partitioning unit 22 may be configured to classify the multi-bit memory cell on the adjacent word line of the to-be-read multi-bit memory cell into one of the N+1 sampling reading value partitions according to the reading value;

The offset flag obtaining unit 23 may be configured to obtain an offset flag corresponding to the classified sampling reading value partition.

It should be noted that when the at least one sampling voltage includes one sampling voltage, there may be two sampling reading value partitions corresponding to the sampling voltage, and each of the sampling reading value partitions corresponds to a respective offset flag. Since the offset flag is represented by log₂ (N+1) bits, only one bit is required to represent the offset flag at this time, and the offset flag is stored in a program block latch of the memory device and has a value of 0 and a value of 1. When the at least one sampling voltage includes three sampling voltages, there may be four sampling reading value partitions corresponding to the sampling voltages, and two bits are required to represent the offset flag at this time, which has a value of 00, a value of 01, a value of 10, and a value of 11.

(3) Reading Module 30

The reading module 30 is configured to read the to-be-read multi-bit memory cell in the reading step S103; that is, the reading module 30 is configured to read the to-be-read multi-bit memory cell according to the multi-level preset read voltages and the at least one read offset of each of the multi-level preset read voltages, each corresponding to a respective one of the at least one offset flag.

Referring to FIG. 4, the reading module 30 may include a determination unit 31 and a performing unit 32.

The determination unit 31 may be configured to determine a current read offset of a preset read voltage of a level corresponding to the offset flag.

The performing unit 32 may be configured to perform a reading of the to-be-read multi-bit memory cell with a voltage that is a sum of the preset read voltage of the level corresponding to the offset flag and the current read offset.

It should be noted that when the at least one sampling voltage includes N sampling voltages, each of the multi-level preset read voltages has (N+1)-level read offsets, and a first-level read offset of the N+1 read offsets is 0. For example, when the at least one sampling voltage includes one sampling voltage, two-level read offsets may be set, and a first-level read offset of the two-level read offsets is 0. When the at least one sampling voltage includes three sampling voltages, fourth-level read offsets may be set, and a first-level read offset of the fourth-level read offsets is 0. Further, the read offsets include one of a voltage offset value and a voltage offset time.

In some implementations, the offset flag may be stored in a program block latch of the memory device; further, when the sample voltages include N sampling voltages, the program block latch may have log₂ (N+1) data bits for storing the offset flag.

Further, the voltage compensation device may be applicable to an operation of reading a low page(s) of the memory device, an operation of reading an intermediate page(s) of the memory device, and an operation of reading a high page(s) of the memory device.

In some implementations, according to the voltage compensation device, ESUM can be improved to 120 mV.

In contrast to the related art, the present disclosure provides a voltage compensation device applied to a memory device. The memory device includes a plurality of word lines and a plurality of multi-bit memory cells connected to the plurality of word lines, and the multi-bit memory cells are configured such that stored values of the multi-bit memory cells are read through multi-level preset read voltages. The voltage compensation device includes a definition module 10, an offset setting module 20, and a reading module 30. The definition module 10 is configured to define at least one read offset for each of the multi-level preset read voltages respectively; the offset setting module 20 is configured to select at least one of the multi-level preset read voltages as the at least one sampling voltage, read a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell, and set at least one offset flag, each representing a size of a respective one of the at least one read offset according to a sampling reading value of the a respective one of the at least one sampling voltage; and the reading module 30 is configured to read the to-be-read multi-bit memory cell according to the multi-level preset read voltages and the at least one read offset of each of the multi-level preset read voltages, each corresponding to a respective one of the at least one offset flag, Thus, the preset read voltages of the to-be-read multi-bit memory cell can be compensated, thereby effectively solving the problem of shift of threshold voltages of the to-be-read multi-bit memory cell that is caused when the adjacent word line of the to-be-read multi-bit memory cell of the memory device is being programmed.

In addition to the aforementioned implementations, there may be other implementations of the present disclosure. All technical solutions formed by equivalent replacements or equivalent substitutions fall within the scope of the present disclosure.

In summary, although the implementations of the present disclosure have been disclosed above, the aforementioned implementations are not intended to limit the present disclosure, and a person of ordinary skill in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure is subject to the scope defined by the claims.

Claims

1. A method for reading a memory device, wherein the memory device comprises a first word line, a second word line, and memory cells, the memory cells comprise first memory cells coupled to the first word line and second memory cells coupled to the second word line, each of the memory cells being configured to storing M bits data, and M is a positive integer greater than or equal to 2, the method comprising: applying at least one first voltage to the first word line; andafter applying the at least one first voltage to the first word line, performing a read operation of reading a first level of 2M levels of the second memory cells, comprising: performing a first read operation based on a first condition; andperforming a second read operation based on a second condition,wherein the first condition is different from the second condition, and the first condition and the second condition comprise a voltage or a time.

2. The method of claim 1, further comprising: applying a second voltage to the second word line during the first read operation; andapplying a third voltage to the second word line during the second read operation,wherein the third voltage is a sum of the second voltage and a first offset, the first offset is based on a reading value of the first memory cells obtained by applying the at least one first voltage to the first word line.

3. The method of claim 2, wherein the at least one first voltage comprises N first voltages, the 2M levels are divided into N+1 partitions, and N is a positive integer greater than or equal to 1.

4. The method of claim 3, wherein the first offset comprises N offsets.

5. The method of claim 2, further comprising: applying a fourth voltage to the second word line to read a second level of the 2M levels of the second memory cells; andapplying a fifth voltage to the second word line to read the second level of the 2M levels of the second memory cells,wherein the fifth voltage is a sum of the fourth voltage and a second offset different from the first offset.

6. The method of claim 5, wherein the fourth voltage is greater than the second voltage, and the second offset is less than the first offset.

7. The method of claim 5, wherein the first offset and the second offset are in a range of 50 mv-80 mv.

8. The method of claim 2, wherein the second voltage is one of the at least one first voltage.

9. The method of claim 3, wherein M=3, N=1, the first to fourth level of the eight levels are in a first partition of the two partitions, and the fifth to eighth level of the eight levels are in a second partition of the two partitions.

10. The method of claim 9, further comprising: storing two offset flags in a latch of the memory device, wherein one of the two partitions corresponds to a respective one of the two offset flags, and the two offset flags are a value of 0 and a value of 1.

11. The method of claim 10, wherein one of the two offset flags corresponds to an offset is 0.

12. The method of claim 1, wherein the first word line and the second word line are adjacent.

13. A memory device, comprising: a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the memory cell array comprises a first word line, a second word line, and memory cells, the memory cells comprise first memory cells coupled to the first word line and second memory cells coupled to the second word line, each of the memory cells being configured to storing M bits data, and M is a positive integer greater than or equal to 2; andthe peripheral circuit is configured to: apply at least one first voltage to the first word line; andafter applying the at least one first voltage to the first word line, perform a read operation of reading a first level of 2M levels of the second memory cells, comprising: perform a first read operation based on a first condition; andperform a second read operation based on a second condition,wherein the first condition is different from the second condition, and the first condition and the second condition comprise a voltage or a time.

14. The memory device of claim 13, wherein the peripheral circuit is further configured to: apply a second voltage to the second word line during the first read operation; andapply a third voltage to the second word line during the second read operation,wherein the third voltage is a sum of the second voltage and a first offset, and the first offset is based on a reading value of the first memory cells obtained by applying the at least one first voltage to the first word line.

15. The memory device of claim 14, wherein the at least one first voltage comprises N first voltages, the 2M levels are divided into N+1 partitions, and N is a positive integer greater than or equal to 1.

16. The memory device of claim 14, wherein the peripheral circuit is further configured to: apply a fourth voltage to the second word line to read a second level of the 2M levels of the second memory cells; andapply a fifth voltage to the second word line to read the second level of the 2M levels of the second memory cells,wherein the fifth voltage is a sum of the fourth voltage and a second offset different from the first offset.

17. The memory device of claim 16, wherein the fourth voltage is greater than the second voltage, and the second offset is less than the first offset.

18. The memory device of claim 15, wherein M=3, N=1, the first to fourth level of the eight levels are in a first partition of the two partitions, and the fifth to eighth level of the eight levels are in a second partition of the two partitions.

19. The memory device of claim 18, wherein the peripheral circuit is further configured to: Stores two offset flags in a latch of the memory device, wherein one of the two partitions corresponds to a respective one of the two offset flags, the two offset flags are a value of 0 and a value of 1, and one of the two offset flags corresponds to an offset is 0.

20. The memory device of claim 13, wherein the first word line and the second word line are adjacent.