Patent Application
20150059640
This disclosure relates generally to methods for growing III-V materials and more particularly to forming by metalorganic chemical. vapor deposition (MOCVD) column III-V materials in a window formed in a dielectric layer.
As is known in the art, many electronics applications incorporate both silicon and column III-V circuits due to their unique performance characteristics. The silicon circuits are typically CMOS circuits used for digital signals and the column circuits are for microwave, millimeter wave, and optical signals. One structure having both CMOS circuits and column III-V circuits is described in U.S. Pat. No. 8,212,294, with inventors Hoke et al., issued Jul. 3, 2013, and assigned to the same assignee as the present patent application and U.S. Pat. No. 7,994,550, with inventors Bettencourt et al, issued Aug. 9, 2011, and assigned to the same assignee as the present patent application.
As described therein, a silicon substrate has thereon: a dielectric layer (e.g. silicon dioxide layer) residing on a top silicon semiconductor layer having CMOS devices and a second silicon dioxide layer which is disposed between the top silicon semiconductor layer and the substrate. A window is etched through the layers to expose the upper surface portion of the silicon substrate and a column semiconductor material is grown epitaxially over the silicon substrate exposed by the window. Compound semiconductor devices such as high electron mobility transistors (HEMTs) and heterojunction bipolar transistors (HBTs) are themed on the column III-V material.
As is also known in the art, one technique used to form a column III-V epitaxial layer is molecular beam epitaxy (MBE) and another is by metaorganic chemical vapor deposition (MOCVD), a chemical vapor deposition method used to produce single or polycrystalline thin films. Generally, column III-V MOCVD crystal growth takes place at temperatures of a hundred to several hundred degrees higher than MBE growth and at much higher pressure. MOCVD growth is by chemical reaction of pyrolized molecules whereas MBE growth, typically of evaporated elements that then react to form the material. Advantages of MBE due to its lower growth temperature and pressure include the following:
Advantages of MOCVD, on the other hand, particularly for nitride materials, include higher growth rate and wafer diameter scalability. Unfortunately, however, when forming a III-V layer though a window in a dielectric layer (deposited over the silicon layer where the CMOS devices are formed) using MOCVD, the deposition is not uniform. The cause of this non-uniformity is due to the higher growth pressures and temperatures of MOCVD growth as well as the lower reactivity of reagent molecules compared to elemental atoms (as in MBE growth) with the underlying surface. In MOCVD growth, this leads to selective area growth where the reactants deposited on the dielectric fail to nucleate and re-vaporize or have high surface mobility and travel to the window edges (increasing the reactant concentration at the window edges), while at the same time material is successfully deposited in the window. As a result, increased reactant concentration at the edges of windows leads to an enhanced growth rate of III-V material there. Additionally, the growth for smaller windows may be faster than larger windows, dense window areas may grow slower than sparse window areas, and all of the previously mentioned effects above may be at play at once.
The inventors have recognized that this growth non-uniformity is particularly detrimental to heterogeneous integration applications since the degree of III-V growth non-uniformity will likely be heavily dependent on the spacing, size and density of the growth windows. Thus, MOCVD selective epitaxy for heterogeneous integration of GaN and CMOS devices may limit the distribution, spacing and minimum size of device. Thus, these effects may severely limit the ability of MOCVD based growth to arbitrarily place III-V based devices for heterogeneous integration with CMOS.
This may be partially addressed in MOCVD by adjusting the growth temperature and pressure to the point where polycrystalline material is successfully deposited outside the window. However, this may compromise the quality of the device material grown within the windows. The initial nucleation of the device material on the substrate (or other III-V template layer) exposed at the bottom of the window is typically one of the most critical phases of material growth, and the optimum conditions may reside in a very narrow range of growth conditions. As a result, the inventors have decoupled the nucleation of device material (e.g., the column III-V deposited material) from the formation of polycrystalline material on a field region of the dielectric layer adjacent the window.
The inventors have solved this non-uniformity problem by forming a single crystal layer or polycrystalline layer (such as, for example, AlN, Si, Al23, ZrO2, SiC, TiN, or column III-V semiconductor layers such as, for example, GaN or metal such as W) on the surface portions over the amorphous dielectric layer field region (the portion of the dielectric layer outside the window) prior to forming by MOCVD the column III-V material. The formed material may be polycrystalline as deposited, or may be deposited amorphously and recrystallized through thermal treatment prior to the column III-V growth in windows. The layers may be formed by methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, molecular beam epitaxy (MBE), metal organic vapor phase deposition (MOCVD), or by sputtering, for example.
A primary beneficial effect of the single crystal layer or polycrystalline layer is to act as a viable nucleation layer for MOCVD material outside the window area (where the column III-V material typically e-vaporizes or travels to the window edge). This in turn results in the uniform consumption of the MOCVD reactants and therefore the formation of column III-V material in windows having uniform growth rates within and between windows that are largely independent of window size, density and distribution over the wafer. Additionally, the formed layer can act as a diffusion barrier or be formed in combination with other layers to reduce auto-doping of the grown III-V layers. This barrier effect can be further enhanced by depositing the polycrystalline material after windows etching in a manner such that the exposed dielectric layers (such as SiO2 and SiN) and semiconductor layers (such as Si) at the windows edges are covered by the deposited material. Thus, the formed layer's diffusion barrier property and its' ability to act as a site for crystal nucleation (over the field region) combine to suppress unintentional doping of the III-V layers and promote uniform consumption of III-V layer reactant species during MOCVD growth. As a result, doping of the grown III-V material is precisely controlledand any impact that growth. window size/placement/density would have on the uniformity of the grown III-V layer is reduced or eliminated dependent non-uniformity.
In accordance with the present disclosure, a method is provided for depositing a column III-V material over a selected portion of a substrate through a window formed in a dielectric layer disposed over the selected portion of the substrate, the method comprising: forming a single crystal layer or polycrystalline layer over a region of the dielectric layer adjacent to the window; and, growing, by MOCVD, a column III-V material over the single crystal layer or polycrystalline layer and through the window over the selected portion of the substrate.
In one embodiment, the polycrystalline layer is deposited polycrystalline material.
In one embodiment, the polycrystalline layer is deposited on the dielectric layer prior to formation of the window.
In one embodiment, the polycrystalline layer is deposited amorphously and thermally recrystallized prior to formation of the window.
In one embodiment, the polycrystalline layer is deposited amorphously and then thermally re-crystallized to provide a single crystal layer at the bottom of the window to provide a column III-V growth template. The polycrystalline layer in this embodiment is not removed at the bottom of the window prior to column III-V material growth, but is instead grown on as a column III-V growth template since the deposited amorphously and then thermally re-crystallized layer is now a single crystal layer at the bottom of the window. An example of this would be AlN deposited by sputtering or ALD (atomic layer deposition).
In one embodiment, the polycrystalline layer is deposited as a mixture of crystalline (in windows) and polycrystalline (over amorphous dielectric field region outside window) after window formation but prior to column III-V growth. The polycrystalline layer in this embodiment is not removed at the bottom of the window prior to column III-V material growth, but is instead grown on as a column III-V growth template since the deposited amorphously and then thermally re-crystallized amorphously deposited polycrystalline layer is not a single crystal layer at the bottom of the window. An example of this would be AlN deposited by MBE.
In one embodiment, the polycrystalline layer is deposited polycrystalline material on the field dielectric and window edges near completion of windows formation when only a thin residual layer of dielectric remains at the bottom of the window over the column III-V growth template layer or substrate. The polycrystalline layer and residual dielectric layer in the window are then removed to allow growth of the column III-V layer in the window.
In one embodiment, the polycrystalline layer is deposited as an amorphous material on the field dielectric and window edges near completion of window when only a thin residual layer of oxide remains at the bottom of the window over the III-V growth template layer or substrate, The polycrystalline layer is then thermally recrystallized. The polycrystalline layer and residual dielectric layer are then removed in the window to allow growth of the III-V layer in the window.
In one embodiment, the polycrystalline layer is deposited as an amorphous material on the field dielectric and windows edges near completion of window formation when only a thin residual layer of dielectric remains at the bottom of the window over the III-V growth template layer or substrate. The amorphous layer and residual dielectric layer are then removed to allow growth of the III-V layer in the window. The polycrystalline layer is then thermally recrystallized prior to III-V growth.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.
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As noted above, by depositing the polycrystalline layer 20 on the surface portions over the dielectric field region of the dielectric layer 18, prior to forming by MOCVD the column material 24a, 24b, the polycrystalline layer 20 acts as viable nucleation layer for MOCVD material outside the window area (where the column III-V material typically re-vaporizes). This in turn results in the uniform consumption of the MOCVD reactants and therefore the formation column III-V material 24a in the window 22 having uniform growth rates that are largely independent of window size, density and distribution over the wafer. Additionally, the deposited polycrystalline layer 20 can act as diffusion barriers or deposited. in combination with other layers to reduce auto-doping of the grown III-V layers. The use of the deposited polycrystalline layer 20 also providing a diffusion barrier layer that limits unintentional dopant diffusion, and promotes polycrystalline growth in the field or region of interest to further suppress dopant diffusion during the MOCVD process and uses the polycrystalline growth in the field to promote uniform consumption of reactant species during MOCVD growth thereby reducing/eliminating any growth window size/placement/density dependent non-uniformity. The layers 24b and 20 are later removed during device processing or have vias formed in them to allow heterogeneous integration with device present on Si layer 16.
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Next, the polycrystalline layer 20 is first deposited amorphously, by methods such as ALD and plasma enhanced chemical vapor deposition (PECVD), as a layer 20′ in
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After forming the III-V layer as described above in connection with
A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example a single crystal layer may be used in place of the polycrystalline layer 20. For example the single crystal layer may be from a Si donor wafer or other compound semiconductors (such as GaN) that would have been grown epitaxially (by MOCVD or MBE) as a single crystal on a donor wafer and bonded and transferred to the dielectric layer 18 in a fabrication approach similar silicon on insulator (SOI) wafer fabrication. The bonding process could be oxide/oxide wafer bonding or other technique such as anodic bonding. Accordingly, other embodiments are within the scope of the following claims.
