Patent Application
20080248640
The present invention relates generally to semiconductor devices and more particularly to methods for making the same.
Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are polysilicon-oxide-semiconductor field-effect transistors (FETs), wherein a gate contact or electrode is energized to create an electric field in a channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel. A gate dielectric or gate oxide is formed over the channel, and a gate electrode or gate contact is formed over the gate dielectric. The gate electrode is often made from polysilicon rather than metal in manufacturing. The gate dielectric and gate electrode layers are then patterned to form a gate structure overlying the channel region of the substrate.
Continuing trends in semiconductor product manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. Transistor performance may be improved by reducing the distance between the source and the drain regions under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate oxide that is formed over the semiconductor surface. Critical dimension (CD) or gate length continues to be reduced in successive technology generations.
FETs are typically made by first defining active areas in a substrate 10 by forming isolation regions 15 consisting of insulating material like silicon dioxide as shown in
Frequently, L1 is not narrow enough to meet the requirements for a fast transistor speed. Therefore, fabrication methods usually include a resist trimming step in which a plasma etch is used to laterally shrink dimension L1 to a smaller size L2 shown in
Referring to
Problems exist which are associated with the lithography process used to form photoresist lines. One of the shortcomings in state of the art lithography processes is that they are incapable of printing the desired feature size with enough process window. Many semiconductor manufacturers have overcome this problem using a trimming process which laterally shrinks the photoresist line with an etch step.
However, there are also problems associated with trimming photoresist which can degrade gate pattern fidelity and decrease device performance, as well as reliability. Such gate problems include, among others, line notching, line top erosion, and poor step-height induced from STI (shallow trench isolation) CMP (chemical mechanical polishing) coverage, which are strongly correlated to an accumulation of resist stress after the trimming process.
Accordingly, there is a need for improved CMOS transistor gate designs and fabrication techniques by which the benefits of scaling can be achieved while avoiding or reducing the poly gate defects associated with accumulating resist stress induced by the resist trim and etch process.
In one embodiment, the invention is directed to a method of reducing polysilicon gate defects in a semiconductor device, the method comprising forming a gate dielectric layer above a semiconductor body substrate; coating the gate dielectric layer with a resist coating; exposing and developing the resist coating; performing a resist annealing; and trimming and etching the photoresist coating.
In another embodiment, the invention is directed to a semiconductor device having reduced gate defects associated with accumulating resist stress, wherein the gate defects are reduced by annealing a resist coating applied to a substrate body of the semiconductor device.
a-1d depict a prior art process for trimming a photoresist line to provide a small CD in a MOSFET device.
One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. The invention relates to polysilicon gate CMOS devices and fabrication methods. The invention may be employed to enhance the device yield and the device reliability, by mitigating or eliminating the defects associated with resist stress from resist trimming and etching.
Referring initially to
The methods and devices of the invention may be implemented using any type of semiconductor substrate body, including but not limited to bulk semiconductor wafers (e.g., silicon), epitaxial layers formed over a bulk semiconductor, SOI wafers, etc. The substrate 210 has an active area 212 located between two isolation regions 214. Isolation regions may be formed by shallow trench isolation (STI). The STI regions 214 are filled with an insulating material such as silicon dioxide or a low k dielectric material. A gate dielectric layer 216 is formed 102 on substrate 210 using any suitable materials, material thicknesses, and processing steps, including thermal oxidation or deposition or combinations thereof to form a gate dielectric above the semiconductor substrate. For instance, the gate dielectric layer 216 may be formed by chemical vapor deposition (CVD) and may comprise silicon oxide, silicon nitride, or silicon carbide. When gate dielectric layer 216 is silicon oxide, it may also be formed by placing substrate 210 in a thermal oxidation furnace with a dry oxygen ambient at approximately 600° C. to 800° C. Other methods such as RTO (rapid thermal oxidation) may also be used to grow an oxide layer. A polysilicon layer 218 is deposited on dielectric layer 216 by a CVD method. Polysilicon layer 218 may be doped or undoped.
The process sequence 100 continues with the optional step of depositing 104 a hardmask 220 over polysilicon layer 218. The hardmask 220 may comprise silicon rich nitride covered by silicon oxynitride (SiON), silicon dioxide (Si)2), or other material. The optional hardmask 120 functions to protect the polisilicon from etch and minimize reflection of light during patterning steps. In one embodiment, an optional ARC 221 can be applied directly over the polysilicon layer 218 without hardmask 220. In another embodiment, ARC 221 can be deposited over hardmask 220 to improve the process latitude further within a subsequent photoresist patterning process.
Following deposition 104 of the optional hardmask 220 and ARC 221 layers, a photoresist layer 222 is formed and deposited 106. The photoresist layer 222 may be formed using any conventional technique. The photoresist layer 222 is patterned by forming a patterned mask (e.g., photoresist mask) on the underlying layer (polysilicon layer 218 or optional hardmask layer 220) beneath the mask and then etching the layer using the patterned mask as an etch mask. Those skilled in the art understand the process for forming and patterning the photoresist layer 222, and thus no further detail is warranted.
A post-exposure bake 108 of the photoresist 222 is then performed. Bake temperatures will generally be around 130° C. and are dependent on the type of resist. Bake time will vary, and will generally be from about 30 seconds to about 90 seconds. Exposed portions of the photoresist 222 are removed by a developer, while the remaining photoresist 222 retains a pattern.
In the implementation of the invention, a resist anneal or thermal bake process 110 is then performed following post-exposure bake and development 108. The temperature range at which the anneal 110 is performed will be dependent upon the type of photoresist 222 applied. Within this temperature range, the critical dimensions are constant and not sensitive to temperature. Generally, it has been found that the temperature range T1 to T2 will be near but lower than a reflow temperature of the photoresist 222. Reflow temperature is defined as the temperature at which the resist gate length will be increased. The temperature range from T1 to T2 will be dependent on different resist designs, but within a range of 5° C.-7° C. below the reflow temperature. Further operational settings of the annealing process 110 (e.g., time, etc.) may be selected to depend on post-etch results. Generally, the annealing time will be varied from about 30 seconds to about 90 seconds.
Not wishing to be bound by theory, it is thought that a reduction in gate defects may be obtained as the resist trim time is reduced due to post-pattern critical dimension shrinkage after resist annealing and the stiffness of the resist pattern is enhanced by the removal of more solvent from the resist after applying the resist anneal 110 according to the invention. Following the anneal process 110, it has been observed that the resist pattern has a smaller critical dimension, better LER and LWR, higher resist stiffness and a more uniform resist profile. Such improvements have not been observed for traditional hard bake processes, which are performed at temperatures less than 150° C. or less than the glass transition temperature of the photoresist coating after development.
The device then continues through a conventional dry trimming and etch process as is know in the art.
Although the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a, manner similar to the term “comprising”.
