Patent Application
20200279610
The present invention relates to storage of data and, more particularly, to a method for retaining data.
As technology advances, processes for manufacturing chips progress; however, certain problems get worse. For example, data storage apparatus in a NAND flash memory gets shorter, and a NAND flash memory keeps on losing data even when it is turned off.
Referring to
To solve the problem with data storage apparatus, a typical method is to read all the pages of all the blocks once every hour for example. Then, it is determined whether the data should be revived based on the amount of bit errors. However, it takes a very long period of time to complete this process.
Referring to
There is however at least one serious problem with this conventional method for retaining data. This conventional method cannot be executed when the NAND flash memory is not turned on. The NAND flash memory will lose at least some of the data if an off period of the NAND flash memory exceeds data storage apparatus, and such loss of data will not be found until a next time the NAND flash memory is turned on. Moreover, some hosts put NAND flash memories into a sleep mode, and there is no time for executing this conventional method.
The present invention is therefore intended to obviate or at least alleviate the problems encountered in prior art.
It is the primary objective of the present invention to provide a reliable method for retaining data.
To achieve the foregoing objective, the method includes the step of reading threshold voltage and a corresponding retention time limit from a current block. Then, retention time is calculated. Then, it is determined whether the retention time is longer than the retention time limit. A swapping routine is executed if the retention time is longer than the retention time limit. The process returns to the step of calculating the retention time if the retention time is no longer than the retention time limit.
Other objectives, advantages and features of the present invention will be apparent from the following description referring to the attached drawings.
The present invention will be described via detailed illustration of the preferred embodiment versus the prior art referring to the drawings wherein:
Referring to
At S10, the process begins.
At S12, several groups of blocks are selected. For example, five (5) groups of blocks are selected.
Then, at S14, each block of the first group is programmed and erased for 100 times, so that the program/erase count (“PEC”) becomes 100. Each block of the second group is programmed and erased for 200 times, so that the PEC becomes 200. Each block of the third group is programmed and erased for 300 times, so that the PEC becomes 300. Each block of the fourth group is programmed and erased for 400 times, so that the PEC becomes 400. Each block of the fifth group is programmed and erased for 500 times, so that the PEC becomes 500.
Then, at S16, data is written in each page of each block of each group in the form of a single-level cell (“SLC”).
Then, at S18, the threshold voltage distribution of each block is read.
Then, at S20, a last non-zero threshold voltage is recorded.
Then, at S22, the NAND flash memory is baked for a period of time such as several hours. The baking is executed to simulate the elapse of a longer period of time. The baking can however be omitted in another embodiment.
Then, at S24, the threshold voltage distribution of each block of each group is read.
Then, at S26, a last non-zero threshold voltage is recorded.
Then, at S28, a database is built. In specific, at first, a value of drifting is calculated by subtracting the non-zero threshold voltage obtained at S26 from the non-zero threshold voltage obtained at the S20. A table of the values of drifting and the corresponding periods of time is made. Secondly, a drifting rate is calculated by dividing each value of drifting by the corresponding period of time. The drifting rate is an average, and the drifting is actually non-linear. The drifting rates or the table can be used to calculate a period of time (“retention time”) in which the threshold voltage distribution of each block moves to the left.
Referring to
Then, at S32, it is determined whether this is the first time the NAND flash memory is turned on. The process goes to S34 if so, and goes to S40 if otherwise.
At S34, a reference block is selected from the blocks of the NAND flash memory. Only one block is selected. Another block will not be selected until the average PEC reaches a next level. For example, a block is selected when the PEC is 0 in the beginning, and another block is selected only when the PEC reaches 100, and so on. It should be noted that data is written in the reference block in the form of SLC even if data is written in another block in the form of a multiple-level cell (“MLC”).
At S36, retention time Trt is cleared from a retention timer of a volatile memory such as a random access memory (“RAM”). The unit of the retention time Trt is “minute” for example, and the value of the retention time Trt is an integer. Hence, the retention timer is actually a counter that adds 1 to the value of the retention time for every elapsed minute. The first time a user turns on the NAND flash memory apparatus, the retention time Trt might not be zero. Hence, the retention time Trt must be cleared.
Then, at S38, the value of the retention timer and a reference threshold voltage are stored in a non-volatile memory as the retention time Trt. Then, the process goes to S50.
At S40, a threshold voltage is read from the reference block.
Then, at S42, the threshold voltage of the reference block and the data in the database are used to calculate power-off time Toff. Power-off time Toff is measured from the last time the data storage apparatus was turned off.
Then, at S44, the retention time Trt is read. This retention time Trt is the retention time Trt stored in the non-volatile memory the last time the data storage apparatus was turned off.
Then, at S46, new retention time Trt is calculated. This new retention time Trt is equal to the retention time Trt stored in the non-volatile memory the last time the data storage apparatus was turned off plus the power-off time Toff.
Then, at S50, it is determined whether the retention time Trt is longer than data storage apparatus. Data storage apparatus is predicted according to the above-mentioned method for predicting a retention time limit according to the preferred embodiment of the present invention. Data storage apparatus is predicted based on the PEC and the threshold voltage of the corresponding block. The process goes to S52 if so, and goes to S54 if otherwise.
At S52, a swapping routine is executed. The swapping routine includes the steps represented by S74, S76, S78, S80, S82, S84, S86 and S88 referring to
At S54, it is determined whether the data storage apparatus is to be turned off. The process goes to S38 if so, and goes to S56 if otherwise.
At S56, it is determined whether a proper period of time such as one (1) minute has elapsed. The process goes to S58 if so, and returns to S50 if otherwise.
At S58, the retention time Trt is increased by one (1).
Then, at S60, the PEC is divided by a proper number such as 100, and it is determined whether a remainder is zero. The process goes to S34 if so, and returns to S50 if otherwise.
The present invention exhibits several advantages. Firstly, the check is effective and efficient. Secondly, the system immediately predicts when the retention time Trt would exceed the retention time limit, and determines whether to swap after the data storage apparatus is turned on. Thirdly, the system immediately detects that the retention time Trt has exceeded the retention time limit and take proper actions after the data storage apparatus is turned on. Therefore, the present invention retains data better than the prior art.
The present invention has been described via the illustration of the preferred embodiment. Those skilled in the art can derive variations from the preferred embodiment without departing from the scope of the present invention. Therefore, the preferred embodiment shall not limit the scope of the present invention defined in the claims.
