The present invention relates to integrated optical circuits and, in particular, to optical waveguide structures formed in and supported by semiconductor substrates.
There is considerable interest in photonic integrated circuit technologies for both active and passive devices.
It is well known to transport electronic data between a data source and a data destination over an optical data path. The use of fiber-optic communications lines presents one well-known example of an optical data path. Indeed, with the continued development of optical communications technologies, functions previously performed in the electrical domain are now migrating into the optical domain. Optical channels are now replacing electric wires for the communication of electronic data, and optical signal processing is now replacing transistor signal processing for the manipulation of electronic data.
This migration towards optical solutions has even progressed down to the level of the integrated circuit. In this regard, the prior art teaches a number of optical waveguide structures implemented in semiconductor substrates. Compact on-chip optical waveguide structures are recognized to have extensive uses in semiconductor photonics.
As semiconductor integrated circuit process technology shrinks towards nano-scale features it is important for the optical waveguide structures formed in or supported by the integrated circuit substrate to also achieve nano-scale dimensions. However, it is difficult to make well-defined on-chip optical waveguide structures, especially in the nano-scale. In particular, there is a need to form densely populated hollow optical waveguides.
In an embodiment, an optical waveguide comprises: a layer of semiconductor material having a bottom surface, said layer of semiconductor material including at least one hollow optical channel contained within the layer of semiconductor material and extending with a length parallel to the bottom surface, said layer of semiconductor material further having a non-planar top surface including first substantially planar top surface portions on either side of the at least one hollow optical channel and a second curved top surface extending over the at least one hollow optical channel, wherein a lowest portion of an inner surface of the at least one hollow optical channel is positioned below the first substantially planar top surface portions of said layer of semiconductor material.
In an embodiment, an optical waveguide comprises: a first layer of semiconductor material; a second layer of semiconductor material having a bottom surface in contact with the first layer of semiconductor material and further having a top surface; a hollow optical channel contained within the second layer of semiconductor material and extending with a length parallel to the bottom surface; wherein said top surface comprises first top surface portions on either side of the hollow optical channel and a second curved top surface portion extending over the hollow optical channel; wherein a lowest portion of an inner surface of the hollow optical channel is positioned below the first top surface portions; and wherein a highest portion of an inner surface of the hollow optical channel is positioned above the first top surface portions.
In an embodiment, an optical waveguide comprises: a supporting semiconductor substrate having a top surface; and a layer of semiconductor material having a bottom surface in contact with the top surface of the supporting semiconductor substrate, said layer of semiconductor material including at least one hollow optical channel contained within the layer of semiconductor material and extending with a length parallel to the top surface of the supporting semiconductor substrate, said layer of semiconductor material further having a non-planar top surface including first top surface portions on either side of the at least one hollow optical channel and a second top surface extending over the at least one hollow optical channel, wherein a lowest portion of an inner surface of the at least one hollow optical channel is positioned below the first top surface portions of said layer of semiconductor material.
In an embodiment, an optical waveguide comprises: a supporting semiconductor substrate having a top surface; and a layer of semiconductor material having a bottom surface in contact with the top surface of the supporting semiconductor substrate, said layer of semiconductor material including at least one hollow optical channel contained within the layer of semiconductor material and extending with a length parallel to the top surface of the supporting semiconductor substrate, said layer of semiconductor material further having a non-planar top surface including first top surface portions on either side of the at least one hollow optical channel and a second top surface extending over the at least one hollow optical channel, wherein a highest portion of the inner surface of the at least one hollow optical channel is positioned above the first top surface portions of said layer of semiconductor material.
For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:
Reference is now made to
A lithographic process as known in the art is then used to form an opening 110 in the silicon nitride layer 108 and silicon dioxide layer 106 (a SiN/SiO2 hard mask) which extends down to reach at least the top surface of the second silicon (Si) layer 104. The result of the lithographic process is shown in
An epitaxial growth process as known in the art is then performed to grow a silicon-germanium (SiGe) layer 112 on top of the second silicon (Si) layer 104 within the opening 110. This silicon-germanium (SiGe) layer 112 is a sacrificial material layer as will be described in more detail below. The epitaxial growth process continues with the formation of a silicon layer (Si) 114 on top of the silicon-germanium (SiGe) layer 112 within the opening 110. The result of the two step epitaxial growth process is shown in
A lithographic process as known in the art is then used to form a plurality of trenches 116 which define at least one line 118 formed of a remaining portion of the second silicon (Si) layer 104, a remaining portion of the silicon-germanium (SiGe) layer 112 and a remaining portion of the silicon layer 114 as a material strip interposed between adjacent parallel trenches 116. The result of the lithographic process is shown in
An epitaxial growth process as known in the art is then performed to grow a silicon layer (Si) 120 on top of the exposed surfaces of the second silicon (Si) layer 104, the silicon-germanium (SiGe) layer 112 and the silicon layer (Si) 114. The silicon layer (Si) 120 is a conformal layer covering the sides and top of the material strip. The result of the epitaxial growth process is shown in
In an exemplary implementation, the width w of the lines 118 may be of the range of 100 nm to hundreds of nm. The length of the lines 118 (extending perpendicular to the width w) may be of the range of several hundred nanometers to hundreds of microns. The etch selectivity between SiGe and Si can reach >300, under HCl, so the maximum length of the line 118 is decided by the thickness of the Si layer 120 which should typically be several tens of nanometers to several hundred nanometers. A spacing z between adjacent lines 118 may be of the range of several tens of nanometers to tens of microns or more as defined by the photomask.
An etch process as known in the art is then performed to selectively remove the sacrificial material of the silicon-germanium (SiGe) layer 112 from within each of the lines 118. In an embodiment, the etch may comprise an HCl dry etch which is selective to remove SiGe and leave the Si structures in place. The result of the selective etch process is shown in
As an alternative, a wet clean such as hot SC1 (a mix of NH4OH and H2O2) can be used for the selective removal of SiGe, but this technique has significantly lower selectivity than HCl.
An anneal process as known in the art is then performed in order to effectuate a reflow of the silicon structures surrounding the hollow channels 122. In an embodiment, the anneal may comprise an anneal in a hydrogen (H2) atmosphere at a temperature of 700 degrees Celsius for a duration of about 30 minutes to achieve Si reflow. The result of the anneal process is shown in
In a preferred implementation, as a result of the reflow the hollow channels 122 are produced in a manner wherein a lower portion of the channel 122 is positioned below an upper surface of the reflowed second silicon (Si) layer 104.
In an exemplary implementation, the width x of the structures 124 may be of the range of 100 nm to hundreds of nanometers. In an exemplary implementation, the diameter y of the hollow channels 122 within the structures 124 may be of the range of 50 nanometers to hundreds of nanometers. A spacing z between adjacent structures 124 may be of the range of several tens of nanometers to tens of microns.
Although an SOI type substrate is preferred, it will be understood that a non-SOI type substrate including the second silicon (Si) layer 104 (alone or perhaps as an epitaxial growth over an underlying intrinsic or non-intrinsic semiconductor layer) could be used in place of the PD SOI substrate 10. In such a case, the illustrated layers 100 and 102 would either be absent or replaced by the underlying intrinsic or non-intrinsic semiconductor layer.
The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.
This application is a continuation of U.S. application Ser. No. 14/933,095 filed Nov. 5, 2015, which is a continuation of U.S. application Ser. No. 13/901,298 filed May 23, 2013 (now U.S. Pat. No. 9,206,526), the disclosures of which are incorporated by reference.
Number | Name | Date | Kind |
---|---|---|---|
5278103 | Mallon et al. | Jan 1994 | A |
5508234 | Dusablon, Sr. et al. | Apr 1996 | A |
6735370 | Da Silva Marques et al. | May 2004 | B1 |
7133586 | Yegnanarayanan et al. | Nov 2006 | B2 |
7149396 | Schmidt | Dec 2006 | B2 |
7391949 | Schmidt et al. | Jun 2008 | B2 |
7471866 | Dumais et al. | Dec 2008 | B2 |
7653281 | Stepanov et al. | Jan 2010 | B2 |
9059252 | Liu et al. | Jun 2015 | B1 |
9983353 | Liu | May 2018 | B2 |
20020057226 | Koh et al. | May 2002 | A1 |
20030035613 | Huber et al. | Feb 2003 | A1 |
20050089262 | Jenkins et al. | Apr 2005 | A1 |
20070165980 | Jenkins et al. | Jul 2007 | A1 |
20080112454 | Ma | May 2008 | A1 |
20090016666 | Kuo et al. | Jan 2009 | A1 |
20100158437 | Decorby | Jun 2010 | A1 |
20120219250 | Ren et al. | Aug 2012 | A1 |
Number | Date | Country | |
---|---|---|---|
20180239085 A1 | Aug 2018 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 14933095 | Nov 2015 | US |
Child | 15962633 | US | |
Parent | 13901298 | May 2013 | US |
Child | 14933095 | US |