Patent Application
20250078925
This application claims the priority benefit of French Application No. 2309151, filed on Aug. 31, 2023, entitled “Procédé d′écriture dans une mémoire à changement de phase,” which is hereby incorporated herein by reference to the maximum extent allowable by law.
The present disclosure generally concerns electronic circuits and devices, and, in particular, memories. The present disclosure more precisely relates to phase-change memories, and to methods of data writing into phase-change memories.
Data storage is a major industrial challenge. There exist different types of technologies enabling to store data.
Phase-change memories are non-volatile memories which store data by modifying the state of a material contained in each memory element of the memory.
It would be desirable to be able to improve, at least partly, certain aspects of phase-change memories, and, in particular, certain aspects of methods of data writing into phase-change memories.
There exists a need for higher-performance phase-change memories.
There exists a need for phase-change memories having a better endurance, that is, having a longer lifetime.
There exists a need for higher-performance methods of data writing into phase-change memories.
There exists a need for methods of data writing into phase-change memories having a better endurance.
An embodiment overcomes all or part of the disadvantages of known methods of data writing into phase-change memories.
An embodiment provides a method of writing a first group of N data, N being an integer, into a second group of N memory cells of a phase-change memory, wherein each data element of the first group comprises a metadata element, wherein for each writing of data element of the first group into a memory cell of the second group, the value of the metadata element of the data element is modified.
According to an embodiment, at the end of a write cycle, all the metadata of the N data have the same value.
According to an embodiment, the metadata element is a sequencing bit.
According to an embodiment, each memory cell of the second group comprises a plurality of memory elements adapted to each storing one data bit.
According to an embodiment, each data element of the first group is a data word comprising a plurality of data bits.
Another embodiment provides a device adapted to implementing the previously-described method, and comprising a phase-change memory.
The foregoing features and advantages, as well as others, will be described in detail in the rest of the disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:
Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties.
For the sake of clarity, only the steps and elements that are useful for the understanding of the described embodiments have been illustrated and described in detail.
Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements.
In the following description, when reference is made to terms qualifying absolute positions, such as terms “edge”, “back”, “top”, “bottom”, “left”, “right”, etc., or relative positions, such as terms “above”, “under”, “upper”, “lower”, etc., or to terms qualifying directions, such as terms “horizontal”, “vertical”, etc., it is referred, unless specified otherwise, to the orientation of the drawings.
Unless specified otherwise, the expressions “about”, “approximately”, “substantially”, and “in the order of” signify plus or minus 10%, preferably of plus or minus 5%.
The embodiments described hereafter concern a method of writing a group of data into memory cells of a phase-change memory enabling to improve the endurance and, thus, the lifetime, of the phase-change memory. For this purpose, each data element of the data group comprises a metadata element having its value modified at each implementation of the write method.
The use of this metadata element, and, more particularly, the modification of its value at each writing, enables to avoid the use of a memory cell erasing step, that is, a step during which the memory cell has switched back to a state where all its bits are at a reference value, for example value “one”. This enables to decrease the number of operations carried out during a cycle of writing into and/or of erasing of the memory, which enables to increase the memory lifetime.
Electronic device 100 may comprise a processor 101 (CPU) adapted to implementing different processings of data stored in memories and/or supplied by other circuits of device 100.
Electronic device 100 may further comprise one or a plurality of memories 102 (MEM), for example memories of different types, among which, for example, a non-volatile memory, a volatile memory, and/or a read-only memory.
According to an embodiment, electronic device 100 comprises a phase-change memory, or PCM memory. According to an embodiment, a phase-change memory is a non-volatile memory.
There is called in the rest of this description memory element of a phase-change memory a memory unit enabling to store binary information, that is, a data bit, that is, a “one” or a “zero”.
There is called in the rest of this description memory cell of a phase-change memory an assembly of a plurality of memory elements enabling to store a plurality of data bits. According to an embodiment, each memory cell is adapted to storing a data element, or data word, formed of a plurality of data bits.
Electronic device 100 further comprises, for example, a secure element 103 (SE) adapted to processing critical and/or secret data. Secure element 103 may comprise its own processor(s), its own memory or memories, etc.
Electronic device 100 further comprises input/output circuits 104 (IN/OUT) adapted to enabling device 100 to communicate with one or a plurality of external electronic devices.
Electronic device 100 may further comprise different circuits 105 (FCT1) and 106 (FCT2) adapted to carrying out different functions. As an example, circuits 105 and 106 may comprise measurement circuits, data conversion circuits, circuits for controlling electronic or electromechanical equipment, etc.
Electronic device 100 further comprises one or a plurality of data buses 107 adapted to transferring data between its different components.
Data element 200 is a data word comprising a plurality of data bits as previously described.
According to an embodiment, data element 200 comprises bits 201 (DATA) storing a data word, and a metadata element 202 (Sq).
According to an embodiment, metadata element 202 is one or a plurality of bits, preferably one bit. According to a preferred embodiment, metadata element 202 is a sequencing bit. According to an example, metadata element 202 forms part of the most significant bits of data element 200. The use of metadata element 202 is described in relation with
There is considered a group 300 of memory cells C(i), i being an integer varying from 0 to N−1. In the example of
As previously described, each memory cell C(i) is adapted to storing a data element of the type of the data element 200 of
At an initial stage (A), all the memory cells of group 300 are ready to store data. According to an example, all the memory cells of group 300 are in a blank state, and all store a same data element, for example a reference data element such as a data element equal to a binary zero. According to another example, all the memory cells of group 300 already store data which have been written by using the method described herein.
According to an embodiment, in the initial state (A), all the memory cells of group 300 store data having their metadata having a same value. According to a preferred embodiment, the metadata element is a sequencing bit, and in the case shown in
In a state (B), consecutive to the initial state (A), a write cycle starts by the writing of a first data element into a first memory cell of group 300, here memory cell C(0). A data element of the data group is written into the portion of the memory cell storing data word 301, and, according to an embodiment, the value of metadata element 302 is modified.
At a state (C), consecutive to state (B), the write cycle carries on with the writing of the second memory cell of group 300, here memory cell C(1). Thus, another data element of the data group is written into the portion of the memory cell storing the data word 301 of the data element, and the value of the metadata element 302 of the data element is modified.
Similarly, the write cycle continues with the writing of a data element into each memory cell of group 300, by modifying, for each memory cell, the value of the metadata element 302 of the data element. Thus, states (D), (E), and (F) show the writing of the other memory cells of group 300, and more particularly, the modification of the value of their metadata 302.
State (F) shows the final state of the write cycle. All the memory cells of group 300 have been written into, and all store a data element. All the metadata of memory cells C(i) have the same value, that is, here, value one.
At a state (G), consecutive to state (F), a new write cycle can start, and cell C(o) is the first one to be written.
An advantage of using metadata during a write cycle is that it enables to view which memory cell has been written into last. In particular, if a write cycle is interrupted, it is sufficient to find two consecutive memory cells which do not have the same metadata value to know when the cycle has been interrupted.
Another advantage of this embodiment is that it enables to implement data write cycles on memory portions, that is, a set number of memory cells. It may enable to implement a page writing system, such as used with flash-type non-volatile memories, or of eSTM type, that is, memories of Embedded Select in Trench Memory (eSTM) type.
Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art.
Finally, the practical implementation of the described embodiments and variants is within the abilities of those skilled in the art based on the functional indications given hereabove.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2309151 | Aug 2023 | FR | national |
