BACKGROUND OF THE INVENTION
Semiconductor wafers having a thickness of less than 200 μm are particularly suitable for the formation of chip stacks in three-dimensional integration. During manufacture the wafer is fastened to a handling wafer to allow the wafer to be thinned and submitted to further process steps without risk of breaking. The material that fastens the wafer to the handling wafer must be sufficiently inert to chemicals used in the process and must withstand elevated temperatures of typically up to 400° C. as well as low-pressure conditions occurring in deposition and cleaning steps. Furthermore, the subsequent removal of the handling wafer must not adversely affect the integrated devices of the semiconductor wafer.
US 2008/0014715 A1 discloses a method for the processing of wafers. A device wafer is bonded to a carrier wafer, which supports the device wafer only at its edge, where a bonding substance is applied. After further process steps have been performed, the bonding substance is heated, so that the device wafer can be detached from the carrier wafer.
US 2009/0218560 A1 discloses a method of production in which a device wafer is bonded to a carrier wafer only at the perimeter. A fill layer surrounded by a material forming an edge bond is arranged between the device wafer and the carrier wafer. The edge bond can be softened, dissolved or mechanically disrupted to allow the wafers to be separated at or near room temperature.
SUMMARY OF THE INVENTION
The method comprises the steps of providing a device wafer having a main surface including an edge region and providing a carrier having a further main surface including an annular surface region corresponding to the edge region of the device wafer, applying an adhesive in the edge region and/or in the annular surface region, but not on the remaining areas of the main surface and the further main surface, and fastening the device wafer to the carrier by the adhesive. Thereby the main surface is brought into contact with the further main surface inside and outside the edge region, while only the edge region is bonded to the further main surface by the adhesive.
Further process steps can be performed while the device wafer is supported by the carrier. In particular, further process steps may include the production of through-wafer vias. The device wafer is afterwards removed from the carrier.
In a variant of the method the device wafer is removed from the carrier by partially removing the adhesive and then mechanically debonding the device wafer from the carrier.
In a further variant of the method, a recess is formed in the annular surface region of the carrier, and the adhesive is applied in the recess before the device wafer is fastened to the carrier.
In a further variant of the method, a further recess is formed in the vicinity of the annular surface region of the carrier. The further recess may be provided to accommodate surplus adhesive.
In a further variant of the method, a step is formed in the edge region of the device wafer, and the adhesive is applied adjacent to the step. The main surface may especially be provided on a dielectric layer, which forms the step.
In a further variant of the method, the main surface is provided with a roughness preventing the main surface from sticking to the further main surface in an area where no adhesive is applied.
The following is a detailed description of examples of the semiconductor device and of the appertaining method of production.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross section of an arrangement of a device wafer and a carrier during the process of being separated from one another.
FIG. 2 is a cross section of an arrangement of a device wafer and a carrier before being fastened to one another.
FIG. 3 is a cross section according to FIG. 2 after the device wafer and the carrier have been fastened to one another.
FIG. 4 is a cross section according to FIG. 3 after further process steps.
FIG. 5 is a cross section according to FIG. 2 for a further embodiment.
FIG. 6 is a cross section according to FIG. 5 after the device wafer and the carrier have been fastened to one another.
FIG. 7 is a cross section according to FIG. 6 for a further embodiment.
FIG. 8 is a cross section of a further embodiment of the carrier.
DETAILED DESCRIPTION
FIG. 1 is a cross section of an arrangement of a device wafer 1 and a carrier 2 during a process step in which the device wafer 1 is separated from the carrier 2. A main surface 10 of the device wafer 1 faces a further main surface 20 of the carrier 2. In the embodiment shown in FIG. 1, the main surface 10 is a surface of a dielectric layer 8, which is non-adhesive. The dielectric layer 8 may comprise a wiring of an integrated circuit of the device wafer 1, for example. The dielectric layer 8 may serve as an intermetal dielectric between metal layers forming the wiring. The integrated circuit may especially be a CMOS circuit, for example. The main surface 10, which is non-adhesive, may instead be formed by a layer of another material, like a passivation layer, or by the surface of a semiconductor body of the device wafer 1. The dielectric layer 8 is shown in the described embodiments to indicate that the main surface 10 may be that side of the device wafer 1 where the circuit components are integrated. The device wafer 1 may be provided with through-wafer vias 4 and a wiring layer 9 on the surface opposite the carrier 2, for example.
An adhesive 3, which was used to fasten the device wafer 1 to the carrier, is located in an edge region 11 of the main surface 10 of the device wafer 1 and in a corresponding annular surface region 21 of the carrier 2. A recess 5 covering the annular surface region 21 may be provided at the edge of the further main surface 21 for the application of the adhesive 3.
In the embodiments shown in the Figures, the device wafer 1 and the carrier 2 have the same dimensions, but the carrier 2 need not have the same dimension as the device wafer 1. The area of the further main surface 20 which is fastened to the edge region 11 of the device wafer 1 by means of the adhesive 3 is therefore designated as an annular surface region 21, which is not necessarily on the edge of the carrier 2.
In the state of the method represented in FIG. 1, the adhesive 3 has already partially be removed, so that the device wafer 1 can mechanically be detached from the carrier 2 by applying a moderate force. The residues of the adhesive 3 may then be disposed of when the wafer is diced.
The method is further described in conjunction with FIGS. 2 to 4. FIG. 2 is a cross section of an arrangement of a device wafer 1 and a carrier 2 before they are fastened to one another. The elements that correspond to similar elements shown in FIG. 1 are designated with the same reference numerals. At its perimeter, the carrier 2 is provided with a recess 5, which may be a few microns deep, typically 5 μm, for instance, and a few millimeters wide, typically 3 mm, for instance. An adhesive 3 is dispensed exclusively along the perimeter of the carrier 2. The recess 5 enables the application of a sufficiently thick layer of the adhesive 3, which optionally only slightly exceeds the level of the further main surface 21.
FIG. 3 is a cross section according to FIG. 2 after the device wafer 1 and the carrier 2 have been fastened to one another. Any surplus adhesive 3 is pushed outwards when the main surface 10 is approached to the further main surface 20. The bond is effected by the adhesive 3 and is confined to the margin of the device wafer 1. Air that may have been trapped in the unbonded central region between the device wafer 1 and the carrier 2 may pose a risk of an uncontrolled delamination of the device wafer 1 from the carrier 2 during further process steps that are performed at a high temperature. This can be avoided if the bonding takes place under low-pressure conditions and/or at an elevated temperature, which typically prevails in wafer bonding chambers. In this way the main surface 10 and the further main surface 20 are brought into contact with one another, while the bond is confined to the periphery.
Before the device wafer 1 is fastened to the carrier, the main surface 10 may be provided with a determined roughness in order to prevent the main surface 10 from sticking to the further main surface 20 in an area outside the edge region 11, hence in an area where no adhesive 3 is applied and no bonding is desired. The roughness may facilitate the debonding step. On the other hand, if the main surface 10 is sufficiently smooth, an effective support of the device wafer 1 by the carrier 2 is secured, the support being essentially homogeneous over the entire surface.
FIG. 4 is a cross section according to FIG. 3 after further process steps. The elements that correspond to similar elements shown in FIG. 3 are designated with the same reference numerals. The device wafer 1 has been thinned from the rear side opposite the carrier 2 and has been provided with through-wafer vias 4 and a wiring layer 9, which may be a redistribution layer, for example. The thinned device wafer 1 is mechanically stabilized by the carrier 2 during the further process steps. The device wafer 1 can then be removed from the carrier 2. To this end the adhesive 3 may be completely removed by a solvent. The adhesive 3 may instead be only partially removed by the solvent. The boundary of the remaining portion of the adhesive 3 is indicated in FIG. 4 by the dotted line traversing the area representing the adhesive 3. The rest of the adhesive 3 is sufficient to allow a controlled mechanical detachment of the device wafer 1 from the carrier 2 by an application of a comparatively low force. The method step of the mechanical detachment is illustrated in FIG. 1.
FIG. 5 is a cross section according to FIG. 2 for a further embodiment. The elements that correspond to similar elements shown in FIG. 2 are designated with the same reference numerals. In the embodiment according to FIG. 5 the adhesive 3 is applied to the device wafer 1. If the edge region 11 of the main surface 10 is left free from the dielectric layer 8, a step 7 is formed at the edge of the dielectric layer 8. The step 7 can be used to confine the adhesive 3 to the edge region 11, and the step 7 has a function similar to the function of the recess 5 in the preceding embodiment. The adhesive 3 optionally only slightly exceeds the level of the main surface 10.
FIG. 6 is a cross section according to FIG. 5 after the device wafer 1 and the carrier 2 have been fastened to one another. Except for the absence of the recess 5 the arrangement shown in FIG. 6 equals the arrangement according to FIG. 3. Any surplus adhesive 3 is pushed outwards when the main surface 10 is approached to the further main surface 20. The bond is effected by the adhesive 3 and is confined to the margin of the device wafer 1. The main surface 10 and the further main surface 20 are in contact with one another, while the bond is confined to the periphery.
FIG. 7 is a cross section according to FIG. 6 for a further embodiment of the arrangement of the device wafer 1 and the carrier 2. In the example shown in FIG. 7 the device wafer 1 comprises a high surface topography, which may be due to through-wafer vias 4 that are in this case produced before bonding the device wafer 1 to the carrier. The described method does not leave any residues in the region of the high surface topography after debonding, because no adhesive is applied in the central area of the device wafer 1. Cleaning the device wafer 1 is thus not necessary or at least essentially facilitated.
FIG. 8 is a cross section of a further embodiment of the carrier 2, which is here provided with a recess 5 and a further recess 6 in the vicinity of the annular surface region 21 at the edge of the carrier 2. The further recess 6 is not filled with the adhesive 3, but it is provided for the accommodation of surplus adhesive 3, which is thus prevented from being squeezed towards the central area of the carrier 2 when the device wafer 1 is fastened.
The described method enables a temporary bond between a device wafer 1 and a carrier 2 providing an essentially homogeneous support without use of an intermediate layer. Because the bond is effected by an adhesive 3 that is confined to the periphery, the device wafer 1 can easily be detached from the carrier 2, and residues of the adhesive 3 are only left at the margin of the device wafer 1. The method allows various adhesives 3 to be selected, including high-temperature stable adhesives 3, so that process steps can be performed at an elevated temperature while the device wafer 1 is supported by the carrier 2. The carrier 2 supports the device wafer 1 also in the center with no need of an intermediate layer.
Patent Application
20150340264
