The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit. More specifically, the methods include at least two operations. The first operation deposits barrier material via PVD or CVD to provide some coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation.
Integrated circuit (IC) manufacturers have traditionally used aluminum and aluminum alloys, among other metals, as the conductive metal for integrated circuits. While copper has a greater conductivity than aluminum, it has not been used because of certain challenges it presents, including the fact that it readily diffuses into silicon oxide and degrades insulating electrical properties even at very low concentrations. Recently, however, IC manufacturers have been turning to copper because of its high conductivity and electromigration resistance, among other desirable properties. Most notable among the IC metalization processes that use copper is Damascene processing. Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as Cu that cannot readily be patterned by plasma etching.
Damascene processing is a method for forming metal lines on integrated circuits. It involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer (inter-metal dielectric). Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as Cu that cannot readily be patterned by plasma etching. In order to frame the context of this invention, a brief description of a copper dual Damascene process for forming a partially fabricated integrated circuit is described below.
Presented in
As depicted in
The process follows, as depicted in
The dual Damascene process continues, as depicted in
Next, as depicted in
After diffusion barrier 123 is deposited, a seed layer of copper is applied (typically a PVD process) to enable subsequent electrofilling of the features with copper inlay.
Copper routes 125 and 107 are now in electrical contact and form conductive pathways, as they are separated by only by diffusion barrier 123 which is itself somewhat conductive. Although conformal barrier layers are sufficiently conductive for conventional circuitry, with the continuing need for faster (signal propagation speed) and more reliable microchip circuitry, the resistance of conformal barrier layers made of the materials mentioned above is problematic. The resistance of such barrier layers can be from ten to one hundred times that of copper. Thus, to reduce resistance between the copper routes, a portion of the diffusion barrier may be etched away, specifically at the via bottom, in order to expose the lower copper plug. In this way, the subsequent copper inlay can be deposited directly onto the lower copper plug. Conventional methods for etching away diffusion barriers at the bottom of vias (for example, the region of barrier 123 contacting copper inlay 107 in
In addition, conventional etching methods do not address unlanded contact regions. As illustrated in
What is therefore needed are improved methods of forming diffusion barriers on integrated circuit structures, selective methods in which the portion of the diffusion barrier at the bottom of vias is either completely or partially removed without sacrificing the integrity of the diffusion barrier in other regions. In this way, the resistance between inlayed metal conductive routes is reduced.
The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit in which the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. At least part of the first operation is performed in the same reaction chamber as the second operation. Some preferred methods of the invention are entirely done in a single process tool, without breaking vacuum. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In some aspects of the invention, selective etching is also used to remove contaminants under the barrier material, thus obviating a separate preclean operation.
The invention accomplishes simultaneous etch and deposition by creation of unique plasma producing process conditions such that barrier material is etched away in some regions while in other regions barrier material is deposited. Thus, the descriptive term “etch to deposition ratio” or “E/D” is used from herein. More specifically, in the context of a partially fabricated integrated circuit having via and trench surface features, methods described herein provide that E/D varies as a function of the elevation profile of the surface features to which the plasma is applied. Generally, E/D is greatest at the bottom most regions of the wafer surface features and decreases in magnitude as elevation increases.
In this invention, there are three E/D scenarios created by control of process conditions. In the first scenario, E/D is greater than 1 at the via bottom, on the trench step, and on the field region. In the second scenario, E/D is greater than 1 at the via bottom and on the trench step, but less than one on the field region. In the third scenario, E/D is greater than 1 at the via bottom, but less than 1 on the trench step and on the field region. By using these three E/D scenarios, a variety of stack barrier layer structures are realized.
A preferred material for this etch/deposition sputter is tantalum, although the invention is not limited to tantalum. Other materials for which the invention is applicable include but are not limited to titanium, tungsten, cobalt, solid solutions (interstitial forms) of tantalum and nitrogen, and binary nitrides (e.g. TaNx, TiN, WNx). After diffusion barriers of the invention are formed, a metal conductive layer is deposited thereon. Where methods of the invention create a diffusion barrier having no barrier material at the bottom of the vias, the metal conductive layer makes direct contact with exposed metal conductive routes. Thus, one aspect of the invention is a method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate. Such methods may be characterized by the following sequence: (a) depositing a first portion of the diffusion barrier over the surface of the wafer substrate, (b) etching through the first portion of the diffusion barrier at the bottom of a plurality of vias while depositing a second portion of the diffusion barrier elsewhere on the wafer substrate, and (c) depositing the metal conductive layer over the surface of the wafer substrate such that the metal conductive layer contacts an underlying metal layer only at the bottom of the plurality of vias. Preferably at least part of (a) and all of (b) are performed in the same processing chamber. Additionally, the wafer may be precleaned before (a) in some preferred methods. In some preferred embodiments, all of (a)-(c) are performed in the same processing tool.
For unlanded vias (and in some instances for fully landed vias as well), methods of the invention create a diffusion barrier having minimal barrier material at the bottom of the vias. In this case, the resistance of the barrier between the metal conductive layer and underlying metal conductive routes is minimized. Thus, another aspect of the invention is a method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate. Such methods may be characterized by the following sequence: (a) precleaning the wafer substrate, (b) depositing a first portion of the diffusion barrier over the surface of the wafer substrate, (c) etching part-way through the first portion of the diffusion barrier at the bottom of a plurality of vias while depositing a second portion of the diffusion barrier elsewhere on the wafer substrate such that the diffusion barrier has a minimum thickness at the bottom of the plurality of vias, and (d) depositing the metal conductive layer over the surface of the wafer substrate. Preferably at least part of (b) and all of (c) are performed in the same processing chamber. In some preferred embodiments, all of (a)-(d) are performed in the same processing tool.
Preferably methods of the invention are used in Damascene processing in which the metal conductive layer and interconnects are made of copper. In some preferred methods of the invention, the metal conductive layer is a copper seed layer. Preferably seed layers of the invention are formed using PVD, but the invention is not limited in this way. As mentioned, in some methods of the invention, all aspects of a process flow for forming a diffusion barrier and depositing a metal conductive route thereon are done in the same processing tool.
Methods of the invention create diffusion barriers having stack structures. Distinct portions of each stack may be deposited (layered) using PVD, CVD, or other methods. Thus diffusion barriers of the invention may have bilayered or trilayered structures. Preferably, the portions include at least one of tantalum, nitrogen-doped tantalum, tantalum nitride, and titanium silicon nitride. More detail of preferred arrangements for the layering of these materials, methods of depositing, and structure of the diffusion barriers formed therefrom, will be described in the detailed description below.
Methods of the invention create diffusion barriers within integrated circuitry using at least the materials described above. Therefore, another aspect of the invention pertains to an integrated circuit or a partially fabricated integrated circuit. Preferably integrated circuits or partially fabricated integrated circuits of the invention include: a diffusion barrier which covers all surfaces of a plurality of vias and a plurality of trenches except that there is no diffusion barrier material at the bottom of the plurality of vias, and a metal conductive layer provided thereon, such that the metal conductive layer comes in direct contact with a plurality of metal conductive routes at the bottom of the plurality of vias. Particularly (but not necessarily) for unlanded vias, yet another aspect of the invention is an integrated circuit or a partially fabricated integrated circuit comprising: a diffusion barrier which covers all surfaces of a plurality of vias and a plurality of trenches, said diffusion barrier having a thickness of between about 50 and 400 Å on said surfaces except at the bottom of the plurality of vias where there is less than about 50 Å of diffusion barrier material; and a metal conductive layer provided thereon.
These and other features and advantages of the present invention will be described in more detail below with reference to the associated drawings.
In the following detailed description of the present invention, numerous specific embodiments are set forth in order to provide a thorough understanding of the invention. However, as will be apparent to those skilled in the art, the present invention may be practiced without these specific details or by using alternate elements or processes. In other instances well-known processes, procedures and components have not been described in detail so as not to unnecessarily obscure aspects of the present invention.
In this application, the term wafer will be used interchangeably with partially fabricated integrated circuit. One skilled in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. Thus, “wafer”, “wafer substrate”, and “substrate” are all used interchangeably.
As mentioned, the invention finds particular use in Damascene processing.
Also as mentioned, the invention accomplishes simultaneous etch and deposition by creation of unique plasma producing process conditions such that barrier material is etched away in some regions while in other regions barrier material is deposited. More specifically, methods described herein provide that E/D varies as a function of the elevation profile of the surface features to which the plasma is applied. Generally, E/D is greatest at the bottom most regions of the wafer surface features and decreases in magnitude as elevation increases. In this invention, there are three E/D scenarios created by control of process conditions. In the first scenario, E/D is greater than 1 at the via bottom, on the trench step, and on the field region. In this first scenario, deposition of barrier material (occurring simultaneously with etch) occurs only on the side walls of the wafer surface features. In the second scenario, E/D is greater than 1 at the via bottom and on the trench step, but less than one on the field region. In this second scenario, deposition of barrier material (occurring simultaneously with etch) occurs not only on the side walls of the wafer surface features, but also on the field. In the third scenario, E/D is greater than 1 at the via bottom, but less than 1 on the trench step and on the field region. In this third scenario, deposition of barrier material (occurring simultaneously with etch at the via bottom) occurs not only on the side walls but also on the trench and field.
A method 200, of forming diffusion barriers of the invention will now be described with reference to the flow chart of
Referring to
Referring to
Again referring to 201 in
Referring to
Thus, the resulting structure 202 has a diffusion barrier (bilayer) that includes first portion 223 and second portion 227. The diffusion barrier is discontinuous, in that it does not cover copper conductive route 211. Note that even though plasma etch was used and copper route 211 was exposed, the dielectric layers were not exposed to plasma during the method. This is a distinct advantage over conventional diffusion barrier formation methods which involve a plasma etch.
Note also that in some instances it has been experimentally determined that there may be a finite amount of the barrier material (e.g. tantalum) implanted into the copper conductive route surface at the bottom of the via. In this invention, this scenario is still considered to mean “exposed copper” at the via bottom, since the tantalum is implanted into the copper and subsequent copper seed layer or inlay makes direct contact with this “doped” copper surface.
Referring again to
As illustrated in
In the above description, and as illustrated in
In another preferred method of the invention, the first portion of the diffusion barrier will be a bilayer, and once the second portion is deposited a trilayer will result. If the first portion of the diffusion barrier is a bilayer, the bilayer will be made of a first deposited layer and a second deposited layer thereon. Either of the first or second deposited layers of the bilayer may include at least one of tantalum, nitrogen-doped tantalum, tantalum nitride, and titanium silicon nitride. These materials are preferably deposited as mentioned above.
Diffusion barrier stack structures (bilayers, trilayers, etc.) can provide better protection against metal diffusion than single layers due to the combined properties of the individual layers of which they are made. In some cases, multi-layered diffusion barriers can also be made thicker to serve as a fill element. For example, in some low-k dielectric applications, lithography leaves the dielectric with undercuts (notches) or bowing (concavity) in the side walls. These defects can be repaired by deposition of extra barrier material which fills the defects. Judicious combinations of CVD and PVD methods are used to achieve this end. One problem with this approach is the resistance at the via bottom due to multiple layers of barrier material. The instant invention solves this problem. For example, depending on the need, in accordance with
In order to describe formation of diffusion barriers intended primarily (but not necessarily) for unlanded vias, a method 300, of forming diffusion barriers of the invention will now be described with reference to the flow chart of
Referring to
Referring to
Again referring to 303 in
Referring to
Referring again to
As illustrated in
In the above description, and as illustrated in
In another preferred method of the invention, the first portion of the diffusion barrier will be a bilayer, and once the second portion is deposited a trilayer will result. As in the methods for fully landed vias, if the first portion of the diffusion barrier is a bilayer, the bilayer will have a first deposited layer and a second deposited layer thereon. Either of the first or second deposited layers of the bilayer may include at least one of tantalum, nitrogen-doped tantalum, tantalum nitride, and titanium silicon nitride. These materials are preferably deposited as mentioned above.
Alternatively, only layer 326 is etched wholly or partially, leaving layer 325 intact, resulting in a diffusion barrier having a minimum thickness at the bottom of the via. Also, alternatively, second portion 329 can be deposited on the trench and field horizontal surfaces as well as on the side walls.
As mentioned, methods of the invention employ a simultaneous etch/deposition to etch barrier material at the via bottom while depositing barrier material elsewhere on a wafer substrate. As well, various aspects of process flows involve deposition of barrier materials (either by CVD or PVD), precleaning, and degassing operations. In certain preferred embodiments all these process steps are done in the same processing tool. One tool that allows degas, preclean, CVD deposition, and PVD deposition all under the same vacuum is the NOVA Tool available from Novellus Systems of San Jose, Calif. Therefore, once a wafer is in the tool and a vacuum is established, at least in some embodiments, all of the above described process aspects are performed without breaking vacuum. Only sources are changed during the operation, e.g. changing from a CVD source to a PVD source. For example, a wafer is placed into the apparatus, it is degassed, precleaned (for example with an argon plasma), a first deposited layer of barrier material is applied via CVD (e.g. titanium silicon nitride), a second deposited layer is applied via PVD (e.g. tantalum nitride). The first and second deposited layers make the first portion of the diffusion barrier. Finally, a tantalum etch/deposition process is carried out which deposits the second portion of the diffusion barrier and etches at least the bottom of the via, forming the final diffusion barrier structure.
Preferably the simultaneous etch/deposition is carried out using hollow-cathode magnetron (HCM) sputtering. Such devices are described in U.S. Pat. No. 5,482,611, naming Helmer et al. as inventors, U.S. Pat. Nos. 6,179,973 B1 and 6,193,854 B1, naming Lai et al. as inventors, and U.S. Pat. No. 6,217,716 B1 naming Fai Lai as the inventor. If the barrier material to be deposited is tantalum, a tantalum target source is used.
Preferable process conditions for include a pressure of between about 0.1 and 100 mTorr. Argon flows are between about 50 and 300 SCCM (standard cubic centimeters per minute). When E/D>1 is desired both at the bottom of the vias and in the field, a DC source power of between about 1 and 10 kW (low power embodiments) is applied to the tantalum target. When an E/D>1 is desired at the bottom of the vias, but E/D<1 in the field is desired, a DC source power of between about 10 and 30 kW (high power embodiments) is applied to the tantalum target. The m-coil (electromagnetic coil for controlling field shape and thus plasma flux) current used is between about 0.1-2.0 A, preferably about 1 A. The wafer temperature is manipulated using a temperature controlled stage, the wafer temperatures used are between about −100 and 100° C., preferably about −50° C. The wafer is biased with an RF frequency source (located below or in proximity to the stage). For methods where it is intended to etch through vias, the RF frequency is preferably between about 100 kHz and 50 MHz. For methods where it is intended to etch only part way through vias, the RF frequency is preferably between about 100 kHz and 50 MHz. The RF power applied is preferably between about 100 and 500 W. In preferred embodiments, the amount of sputtering is controlled by the RF power at fixed RF frequency. Various RF frequencies can be used to achieve this effect. One preferred RF frequency is 13.56 MHz.
In general, etch rate is most strongly related to the RF power, while the deposition rate is most strongly related to the DC source power. The E/D ratio depends predominantly on the ratio of RF power (table) to DC power (source). The higher the RF/DC power ratio, the higher the E/D ratio on the wafer. The etch rate is largely dependent on RF power and pressure since these parameters control the energy of Ar ions near the wafer. The deposition rate is largely dependent on DC power since this parameter affects the flux and energy of Ar ions near the surface target.
While not wishing to be bound by theory, it is believed that the RF frequency creates anisotropic plasma conditions. The etch/deposition ratio (E/D) can be controlled so that it is >1 in the via bottom and (resulting in a net etching), and >1 or <1 on the trench and field horizontal surfaces. The magnitude of E/D on the side walls is <1 because the plasma flux is directed primarily toward the wafer surface (parallel with the side walls). Thus, only horizontal surfaces (with relatively large surface areas (compared to the side walls)) are effectively etched by the impinging plasma flux. The side walls receive a net deposition.
If tantalum nitride or nitrogen-doped tantalum is the barrier material to be deposited, a nitrogen source such as N2 will be used at 10-100 SCCM, preferably about 30 SCCM in conjunction with argon. Titanium silicon nitride is deposited by CVD using a technique described in U.S. patent application Ser. No. 09/965,471, entitled “Method of Depositing a Diffusion Barrier for Copper Interconnection Applications” filed by Suwwan de Felipe on the same date as this application, or U.S. patent application Ser. No. 09/862,539, titled “Improved Deposition of Conformal Copper Seed Layers by Control of Barrier Layer Morphology” filed by Suwwan de Felipe on May 21, 2001.
As mentioned, methods of the invention form diffusion barriers having stacked structures. Both methods primarily intended for fully landed vias (etch through at via bottom) and methods primarily intended for unlanded vias (partial etch at via bottom) form bilayered and trilayered diffusion barriers. Illustrative structures of diffusion barriers of the invention were described above with reference to the figures. The table below summarizes further aspects of some preferred embodiments of the invention. Each of the twelve listed diffusion barriers may vary according to the particular thickness of the deposited layers, and whether or not material is deposited only on the side walls or on the side walls and the field and horizontal trench regions during the simultaneous etch deposition (E/D) process step. Therefore this table is meant to emphasize some preferred stack compositions as well as particular methods used to form them. The symbol “Ta(N)” is meant to designate tantalum with some nitrogen content. This can be nitrogen-doped tantalum, solid solutions (interstitial forms) of tantalum and nitrogen, or tantalum nitrides. Titanium silicon nitride is designated by “TiN(Si).”
Although various details have been omitted for clarity's sake, various design alternatives may be implemented. Therefore, the present examples are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope of the appended claims.
This application is a division of U.S. patent application Ser. No. 13/904,464 filed May 29, 2013, titled “Method of Depositing a Diffusion Barrier for Copper Interconnect Applications” by Rozbicki et al., which is a continuation of U.S. patent application Ser. No. 12/764,870 filed Apr. 21, 2010 (now abandoned), titled “Method of Depositing a Diffusion Barrier for Copper Interconnect Applications” by Rozbicki et al., which is a continuation of U.S. patent application Ser. No. 11/714,465 filed Mar. 5, 2007 (now U.S. Pat. No. 7,732,314), titled “Method for Depositing a Diffusion Barrier for Copper Interconnect Applications” by Danek et al., which is a continuation of U.S. patent application Ser. No. 10/804,353 filed Mar. 18, 2004 (now U.S. Pat. No. 7,186,648), titled “Barrier First Method For Single Damascene Trench Applications,” naming Rozbicki et al. as inventors, which is a continuation-in-part of U.S. patent application Ser. No. 10/412,562 filed Apr. 11, 2003 (now U.S. Pat. No. 6,764,940), which is a continuation-in-part of U.S. patent application Ser. No. 09/965,472 filed Sep. 26, 2001 (now U.S. Pat. No. 6,607,977), which claims benefit of prior U.S. Provisional Application No. 60/275,803 filed Mar. 13, 2001. U.S. Pat. No. 6,764,940 also claims benefit of U.S. Provisional Patent Application No. 60/379,874 filed May 10, 2002. Each of these references is incorporated herein by reference in its entirety for all purposes.
Number | Name | Date | Kind |
---|---|---|---|
3763031 | Scow et al. | Oct 1973 | A |
3767551 | Lang et al. | Oct 1973 | A |
4058430 | Suntola et al. | Nov 1977 | A |
4392111 | Rostoker | Jul 1983 | A |
4492620 | Matsuo et al. | Jan 1985 | A |
4588490 | Cuomo et al. | May 1986 | A |
4604180 | Hirukawa et al. | Aug 1986 | A |
4609903 | Toyokura et al. | Sep 1986 | A |
4622121 | Wegmann et al. | Nov 1986 | A |
4737384 | Murthy et al. | Apr 1988 | A |
4874493 | Pan | Oct 1989 | A |
4946576 | Dietrich et al. | Aug 1990 | A |
4963524 | Yamazaki | Oct 1990 | A |
4997539 | Komizo et al. | Mar 1991 | A |
4999096 | Nihei et al. | Mar 1991 | A |
5009963 | Ohmi et al. | Apr 1991 | A |
5084412 | Nakasaki | Jan 1992 | A |
5093279 | Andreshak et al. | Mar 1992 | A |
5126028 | Hurwitt et al. | Jun 1992 | A |
5139825 | Gordon et al. | Aug 1992 | A |
5178739 | Barnes et al. | Jan 1993 | A |
5186718 | Tepman et al. | Feb 1993 | A |
5194398 | Miyachi et al. | Mar 1993 | A |
5221449 | Colgan et al. | Jun 1993 | A |
5236868 | Nulman | Aug 1993 | A |
5281485 | Colgan et al. | Jan 1994 | A |
5298091 | Edwards, III et al. | Mar 1994 | A |
5378506 | Imai et al. | Jan 1995 | A |
5431799 | Mosely et al. | Jul 1995 | A |
5482611 | Helmer et al. | Jan 1996 | A |
5582881 | Besser et al. | Dec 1996 | A |
5622608 | Lanford et al. | Apr 1997 | A |
5629221 | Chao et al. | May 1997 | A |
5654233 | Yu | Aug 1997 | A |
5656860 | Lee | Aug 1997 | A |
5738917 | Besser et al. | Apr 1998 | A |
5752395 | Nakamura | May 1998 | A |
5766379 | Lanford et al. | Jun 1998 | A |
5789027 | Watkins et al. | Aug 1998 | A |
5801089 | Kenney | Sep 1998 | A |
5891513 | Dubin et al. | Apr 1999 | A |
5904565 | Nguyen et al. | May 1999 | A |
5948215 | Lantsman | Sep 1999 | A |
5962923 | Xu et al. | Oct 1999 | A |
5969422 | Ting et al. | Oct 1999 | A |
5985762 | Geffken et al. | Nov 1999 | A |
6020258 | Yew et al. | Feb 2000 | A |
6037257 | Chiang et al. | Mar 2000 | A |
6037258 | Liu et al. | Mar 2000 | A |
6046108 | Liu et al. | Apr 2000 | A |
6051114 | Yao et al. | Apr 2000 | A |
6074544 | Reid et al. | Jun 2000 | A |
6077403 | Kobayashi et al. | Jun 2000 | A |
6077780 | Dubin | Jun 2000 | A |
6080285 | Liu et al. | Jun 2000 | A |
6093966 | Venkatraman et al. | Jul 2000 | A |
6099702 | Reid et al. | Aug 2000 | A |
6100200 | Van Buskirk et al. | Aug 2000 | A |
6105078 | Crockett et al. | Aug 2000 | A |
6110346 | Reid et al. | Aug 2000 | A |
6114238 | Liao | Sep 2000 | A |
6120641 | Stevens et al. | Sep 2000 | A |
6124203 | Joo et al. | Sep 2000 | A |
6126798 | Reid et al. | Oct 2000 | A |
6133143 | Lin et al. | Oct 2000 | A |
6139712 | Patton et al. | Oct 2000 | A |
6147000 | You et al. | Nov 2000 | A |
6156167 | Patton et al. | Dec 2000 | A |
6159354 | Contolini et al. | Dec 2000 | A |
6159857 | Liu et al. | Dec 2000 | A |
6162344 | Reid et al. | Dec 2000 | A |
6176983 | Bothra et al. | Jan 2001 | B1 |
6179973 | Lai et al. | Jan 2001 | B1 |
6179983 | Reid et al. | Jan 2001 | B1 |
6193854 | Lai et al. | Feb 2001 | B1 |
6193855 | Gopairaja et al. | Feb 2001 | B1 |
6200893 | Sneh | Mar 2001 | B1 |
6203613 | Gates et al. | Mar 2001 | B1 |
6217716 | Fai Lai | Apr 2001 | B1 |
6221757 | Schmidbauer et al. | Apr 2001 | B1 |
6228236 | Rosenstein et al. | May 2001 | B1 |
6228754 | Iacoponi et al. | May 2001 | B1 |
6235163 | Angelo et al. | May 2001 | B1 |
6249055 | Dubin | Jun 2001 | B1 |
6251242 | Fu et al. | Jun 2001 | B1 |
6258707 | Uzoh | Jul 2001 | B1 |
6265313 | Huang et al. | Jul 2001 | B1 |
6271591 | Dubin et al. | Aug 2001 | B1 |
6274008 | Gopalraja et al. | Aug 2001 | B1 |
6277249 | Gopalraja et al. | Aug 2001 | B1 |
6280597 | Kashiwada et al. | Aug 2001 | B1 |
6287977 | Hashim et al. | Sep 2001 | B1 |
6306732 | Brown | Oct 2001 | B1 |
6333547 | Tanaka et al. | Dec 2001 | B1 |
6335288 | Kwan et al. | Jan 2002 | B1 |
6340435 | Bjorkman et al. | Jan 2002 | B1 |
6342133 | D'Couto et al. | Jan 2002 | B2 |
6342448 | Lin et al. | Jan 2002 | B1 |
6350353 | Gopalraja et al. | Feb 2002 | B2 |
6358376 | Wang et al. | Mar 2002 | B1 |
6372301 | Narasimhan et al. | Apr 2002 | B1 |
6383920 | Wang et al. | May 2002 | B1 |
6387805 | Ding et al. | May 2002 | B2 |
6391727 | Park | May 2002 | B1 |
6391785 | Satta et al. | May 2002 | B1 |
6395642 | Liu et al. | May 2002 | B1 |
6398929 | Chiang et al. | Jun 2002 | B1 |
6399479 | Chen et al. | Jun 2002 | B1 |
6402907 | Rich | Jun 2002 | B1 |
6417094 | Zhao et al. | Jul 2002 | B1 |
6423200 | Hymes | Jul 2002 | B1 |
6436251 | Gopalraja et al. | Aug 2002 | B2 |
6440854 | Rozbicki | Aug 2002 | B1 |
6444104 | Gopalraja et al. | Sep 2002 | B2 |
6446572 | Brcka | Sep 2002 | B1 |
6448176 | Grill et al. | Sep 2002 | B1 |
6448657 | Dorleans | Sep 2002 | B1 |
6451177 | Gopalraja et al. | Sep 2002 | B1 |
6492262 | Uzoh | Dec 2002 | B2 |
6498091 | Chen et al. | Dec 2002 | B1 |
6500762 | Hashim et al. | Dec 2002 | B2 |
6508919 | Licata et al. | Jan 2003 | B1 |
6509267 | Woo et al. | Jan 2003 | B1 |
6518668 | Cohen | Feb 2003 | B2 |
6534394 | Cooney, III et al. | Mar 2003 | B1 |
6538324 | Tagami et al. | Mar 2003 | B1 |
6541371 | Ashtiani et al. | Apr 2003 | B1 |
6541374 | de Felipe et al. | Apr 2003 | B1 |
6554914 | Rozbicki et al. | Apr 2003 | B1 |
6559061 | Hashim et al. | May 2003 | B2 |
6562715 | Chen et al. | May 2003 | B1 |
6566246 | de Felipe et al. | May 2003 | B1 |
6589887 | Dalton et al. | Jul 2003 | B1 |
6596133 | Mosiehi et al. | Jul 2003 | B1 |
6605534 | Chung et al. | Aug 2003 | B1 |
6607977 | Rozbicki et al. | Aug 2003 | B1 |
6607982 | Powell et al. | Aug 2003 | B1 |
6613199 | Tobin et al. | Sep 2003 | B1 |
6624066 | Lu et al. | Sep 2003 | B2 |
6642146 | Rozbicki et al. | Nov 2003 | B1 |
6652718 | D'Couto et al. | Nov 2003 | B1 |
6656841 | Kim | Dec 2003 | B1 |
6660622 | Chen et al. | Dec 2003 | B2 |
6673716 | D'Couto et al. | Jan 2004 | B1 |
6683425 | Lai | Jan 2004 | B1 |
6706142 | Savas et al. | Mar 2004 | B2 |
6706155 | Morimoto et al. | Mar 2004 | B2 |
6709557 | Kailasam et al. | Mar 2004 | B1 |
6709987 | Hashim et al. | Mar 2004 | B2 |
6740580 | Gupta et al. | May 2004 | B1 |
6755945 | Yasar et al. | Jun 2004 | B2 |
6758947 | Chiang et al. | Jul 2004 | B2 |
6764940 | Rozbicki et al. | Jul 2004 | B1 |
6777334 | Shiu et al. | Aug 2004 | B2 |
6784096 | Chen et al. | Aug 2004 | B2 |
6790776 | Ding et al. | Sep 2004 | B2 |
6797608 | Lin | Sep 2004 | B1 |
6841044 | Ruzic | Jan 2005 | B1 |
6881664 | Catabay et al. | Apr 2005 | B2 |
6893541 | Chiang et al. | May 2005 | B2 |
6905965 | Subrahmanyan et al. | Jun 2005 | B2 |
6919275 | Chiang et al. | Jul 2005 | B2 |
6943111 | Lin et al. | Sep 2005 | B2 |
6949457 | Fiordalice et al. | Sep 2005 | B1 |
6969448 | Lau | Nov 2005 | B1 |
6992012 | Hashim et al. | Jan 2006 | B2 |
7014887 | Cohen et al. | Mar 2006 | B1 |
7030031 | Wille et al. | Apr 2006 | B2 |
7037830 | Rumer et al. | May 2006 | B1 |
7048837 | Somekh et al. | May 2006 | B2 |
7070687 | Chikarmane et al. | Jul 2006 | B2 |
7074714 | Chiang et al. | Jul 2006 | B2 |
7135402 | Lin et al. | Nov 2006 | B2 |
7186648 | Rozbicki et al. | Mar 2007 | B1 |
7253109 | Ding et al. | Aug 2007 | B2 |
7294574 | Ding et al. | Nov 2007 | B2 |
7365001 | Yang et al. | Apr 2008 | B2 |
7381639 | Chiang et al. | Jun 2008 | B2 |
7452743 | Oliver et al. | Nov 2008 | B2 |
7510634 | Klawuhn et al. | Mar 2009 | B1 |
7517801 | Takeshita | Apr 2009 | B1 |
7576002 | Chen et al. | Aug 2009 | B2 |
7645696 | Dulkin et al. | Jan 2010 | B1 |
7659197 | Juliano | Feb 2010 | B1 |
7682966 | Rozbicki et al. | Mar 2010 | B1 |
7732314 | Danek et al. | Jun 2010 | B1 |
7745332 | Shaviv et al. | Jun 2010 | B1 |
7781327 | Kailasam et al. | Aug 2010 | B1 |
7842605 | Phadhan et al. | Nov 2010 | B1 |
7855147 | Dulkin et al. | Dec 2010 | B1 |
7897516 | Kinder et al. | Mar 2011 | B1 |
7922880 | Phadhan et al. | Apr 2011 | B1 |
7964504 | Shaviv et al. | Jun 2011 | B1 |
8017523 | Wu et al. | Sep 2011 | B1 |
8043484 | Rozbicki | Oct 2011 | B1 |
8298933 | Shaviv et al. | Oct 2012 | B2 |
8298936 | Rozbicki et al. | Oct 2012 | B1 |
8449731 | Pradhan et al. | May 2013 | B1 |
8679972 | Rozbicki et al. | Mar 2014 | B1 |
8765596 | Pradhan et al. | Jul 2014 | B1 |
8858763 | Klawuhn et al. | Oct 2014 | B1 |
20010039113 | Blalock et al. | Nov 2001 | A1 |
20020000382 | Morrissey et al. | Jan 2002 | A1 |
20020028576 | Hashim et al. | Mar 2002 | A1 |
20020029958 | Chiang et al. | Mar 2002 | A1 |
20020034874 | Aoki | Mar 2002 | A1 |
20020041028 | Choi et al. | Apr 2002 | A1 |
20020047128 | Song et al. | Apr 2002 | A1 |
20020110999 | Lu et al. | Aug 2002 | A1 |
20020115287 | Hashim et al. | Aug 2002 | A1 |
20020162736 | Ngo et al. | Nov 2002 | A1 |
20020182847 | Yokoyama et al. | Dec 2002 | A1 |
20030034244 | Yasar et al. | Feb 2003 | A1 |
20030034251 | Chikarmane et al. | Feb 2003 | A1 |
20030116427 | Ding et al. | Jun 2003 | A1 |
20030129828 | Cohen | Jul 2003 | A1 |
20030216035 | Rengarajan et al. | Nov 2003 | A1 |
20040007325 | Pan et al. | Jan 2004 | A1 |
20040048461 | Chen | Mar 2004 | A1 |
20040094402 | Gopalraja et al. | May 2004 | A1 |
20040134769 | Wang et al. | Jul 2004 | A1 |
20040152301 | Hashim et al. | Aug 2004 | A1 |
20040171250 | Chiang et al. | Sep 2004 | A1 |
20040188239 | Robison et al. | Sep 2004 | A1 |
20040211661 | Zhang et al. | Oct 2004 | A1 |
20040216762 | Lo et al. | Nov 2004 | A1 |
20040224507 | Marieb et al. | Nov 2004 | A1 |
20040266175 | Chen et al. | Dec 2004 | A1 |
20050006222 | Ding et al. | Jan 2005 | A1 |
20050020080 | Chiang et al. | Jan 2005 | A1 |
20050032382 | Rossman | Feb 2005 | A1 |
20050048767 | Matsumoto | Mar 2005 | A1 |
20050085068 | Chiang et al. | Apr 2005 | A1 |
20050085070 | Park | Apr 2005 | A1 |
20050103620 | Chistyakov | May 2005 | A1 |
20050106865 | Chung et al. | May 2005 | A1 |
20050110147 | Wu et al. | May 2005 | A1 |
20050127511 | Yang et al. | Jun 2005 | A1 |
20050173239 | Somekh et al. | Aug 2005 | A1 |
20050186793 | Omoto et al. | Aug 2005 | A1 |
20050211545 | Cerio, Jr. et al. | Sep 2005 | A1 |
20050252765 | Zhang et al. | Nov 2005 | A1 |
20050255690 | Chen et al. | Nov 2005 | A1 |
20050255691 | Ding et al. | Nov 2005 | A1 |
20050255700 | Gopalraja et al. | Nov 2005 | A1 |
20050266682 | Chen et al. | Dec 2005 | A1 |
20050272254 | Ding et al. | Dec 2005 | A1 |
20050275110 | Maekawa et al. | Dec 2005 | A1 |
20050282378 | Fukunaga et al. | Dec 2005 | A1 |
20060014378 | Aggarwal et al. | Jan 2006 | A1 |
20060024953 | Rao et al. | Feb 2006 | A1 |
20060030151 | Ding et al. | Feb 2006 | A1 |
20060057843 | Chen et al. | Mar 2006 | A1 |
20060073700 | Brown et al. | Apr 2006 | A1 |
20060125100 | Arakawa | Jun 2006 | A1 |
20060148253 | Chung et al. | Jul 2006 | A1 |
20060166448 | Cohen | Jul 2006 | A1 |
20060207873 | Fu | Sep 2006 | A1 |
20060258152 | Haider | Nov 2006 | A1 |
20060286764 | Zhang et al. | Dec 2006 | A1 |
20070020922 | Chiang et al. | Jan 2007 | A1 |
20070059925 | Choi et al. | Mar 2007 | A1 |
20070085211 | Hamada | Apr 2007 | A1 |
20070141831 | Maekawa et al. | Jun 2007 | A1 |
20070178682 | Chiang et al. | Aug 2007 | A1 |
20070184652 | Frank et al. | Aug 2007 | A1 |
20070193982 | Brown et al. | Aug 2007 | A1 |
20070197012 | Yang et al. | Aug 2007 | A1 |
20070197021 | Nam et al. | Aug 2007 | A1 |
20070222078 | Furuya | Sep 2007 | A1 |
20070238279 | Cerio, Jr. | Oct 2007 | A1 |
20070252277 | Tsao et al. | Nov 2007 | A1 |
20070257366 | Wang et al. | Nov 2007 | A1 |
20070283886 | Chung et al. | Dec 2007 | A1 |
20080067680 | Sakai et al. | Mar 2008 | A1 |
20080110747 | Ding et al. | May 2008 | A1 |
20080142359 | Gopalraja et al. | Jun 2008 | A1 |
20080190760 | Tang et al. | Aug 2008 | A1 |
20080310005 | Tonar et al. | Dec 2008 | A1 |
20090233438 | Ding et al. | Sep 2009 | A1 |
20100009533 | Pradhan et al. | Jan 2010 | A1 |
Number | Date | Country |
---|---|---|
1567548 | Jan 2005 | CN |
0 692 551 | Jan 1996 | EP |
56157037 | Dec 1981 | JP |
09082696 | Mar 1997 | JP |
11-186273 | Sep 1999 | JP |
2008-308765 | Dec 2008 | JP |
WO9927579 | Jun 1999 | WO |
Entry |
---|
U.S. Declaration of Interference dated May 25, 2012, Patent Interference No. 105,898 (U.S. Pat. 6,607,977 vs. U.S. Appl. No. 11/733,671). |
U.S. Resubmission of Request for Declaration of Interference dated Apr. 10, 2007, U.S. Pat. 6,607,977 vs. U.S. Appl. No. 11/733,671. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, Chiang List of Proposed Motions, Aug. 20, 2012. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, BPAI Decision on Motions, Jun. 26, 2013. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, BPAI Judgment on Priority, Jul. 30, 2013. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, BPAI Decision on Request for Rehearing, Jul. 16, 2013. |
Brief of Appellants filed Dec. 20, 2013, Rozbicki v. Chiang, U.S. Court of Appeals for the Federal Circuit, Case No. 2014-1041. |
Brief of Appellees filed Feb. 12, 2014, Rozbicki v. Chiang, U.S. Court of Appeals for the Federal Circuit, Case No. 2014-1041. |
Reply Brief Of Appellants filed Mar. 3, 2014, Rozbicki v. Chiang, U.S. Court of Appeals for the Federal Circuit, Case No. 2014-1041. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, Rozbicki Motion 1 (for Judgment that Claims are Unpatentable), Sep. 11, 2012. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, Rozbicki Motion 2 (to Deny Chiang Benefit of its Earlier Filed Applications), Sep. 11, 2012. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, Chiang Opposition 1, Nov. 21, 2012. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, Chiang Opposition 2, Nov. 21, 2012. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, Rozbicki Reply 1, Jan. 17, 2013. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, Rozbicki Reply 2, Jan. 17, 2013. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, Chiang Miscellaneous Motion 1, Feb. 19, 2013. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, Rozbicki Opposition 1, Mar. 8, 2013. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, Chiang Miscellaneous Reply 1, Mar. 14, 2013. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, Rozbicki Miscellaneous Motion 3, Jul. 10, 2013. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, Decision on Motion, Mar. 12, 2015. |
Rozbicki et al. v. Chiang et al., Patent Interference 105,898, Judgment, Mar. 12, 2015. |
US Office Action dated Jan. 26, 2015 in U.S. Appl. No. 13/619,077. |
U.S. Appl. No. 12/764,870, filed Apr. 21, 2010, entitled “Barrier First Method for Single Damascene Trench Applications.” |
U.S. Appl. No. 12/391,719, filed Feb. 24, 2009, entitled “Apparatus and Methods for Deposition and/or Etch Selectivity”. |
U.S. Appl. No. 11/564,222, filed Nov. 28, 2006, entitled “Method and Apparatus for Controlling Sputtered Flux in PVD Sources.” |
U.S. Appl. No. 11/977,355, filed Oct. 23, 2007, entitled “A Method of Enhancing Selectivity of Resputtering Process.” |
U.S. Appl. No. 12/699,738, filed Feb. 3, 2010, entitled “Multistep Method of Depositing Metal Seed Layers.” |
U.S. Appl. No. 13/033,349, filed Feb. 23, 2011, entitled “Method and Apparatus for Increasing Local Plasma Density in Magnetically Confined Plasma.” |
U.S. Appl. No. 13/619,077, filed Sep. 14, 2012, entitled “Conformal Films on Semiconductor Substrates.” |
U.S. Appl. No. 12/910,623, filed Oct. 22, 2010, entitled “Atomic Layer Profiling of Diffusion Barrier and Metal See Layers.” |
U.S. Appl. No. 12/154,984, filed May 28, 2008, entitled “Methods and Apparatus for Depositing Titanium Based Diffusion Barrier Films.” |
Chiang et al., U.S. Appl. No. 08/978,792, filed Nov. 26, 1997. |
U.S. Appl. No. 11/131,599, filed May 18, 2005, entitled “Gas Treatment Method and Apparatus to Improve Copper Gap Fill.” |
US Office Action, dated Jul. 31, 2002, issued in U.S. Appl. No. 09/862,539. |
US Office Action, dated Apr. 22, 2002, issued in U.S. Appl. No. 09/776,704. |
US Final Office Action, dated Sep. 16, 2002, issued in U.S. Appl. No. 09/776,704. |
US Office Action, dated Oct. 4, 2002, issued in U.S. Appl. No. 09/816,847. |
US Final Office Action, dated Apr. 3, 2003, issued in U.S. Appl. No. 09/816,847. |
US Office Action, dated Oct. 23, 2002, issued in U.S. Appl. No. 09/965,472. |
US Notice of Allowance, dated Mar. 24, 2003, issued in U.S. Appl. No. 09/965,472. |
US Office Action, dated Oct. 3, 2003, issued in U.S. Appl. No. 10/412,562. |
US Notice of Allowance, dated Apr. 13, 2004, issued in U.S. Appl. No. 10/412,562. |
US Office Action, dated Oct. 3, 2005, issued in U.S. Appl. No. 10/804,353. |
US Final Office Action, dated Mar. 23, 2006, issued in U.S. Appl. No. 10/804,353. |
US Notice of Allowance, dated Oct. 3, 2006, issued in U.S. Appl. No. 10/804,353. |
US Office Action, dated Dec. 12, 2008, issued in U.S. Appl. No. 11/714,465. |
US Office Action, dated Aug. 3, 2009, issued in U.S. Appl. No. 11/714,465. |
US Notice of Allowance, dated Mar. 8, 2010, issued in U.S. Appl. No. 11/714,465. |
US Office Action, dated Apr. 14, 2011, issued in U.S. Appl. No. 12/764,870. |
US Final Office Action, dated Nov. 16, 2011, issued in U.S. Appl. No. 12/764,870. |
US Notice of Allowance, dated May 11, 2012, issued in U.S. Appl. No. 12/764,870. |
US Notice of Allowance, dated Aug. 20, 2012, issued in U.S. Appl. No. 12/764,870. |
US Office Action, dated Nov. 30, 2012, issued in U.S. Appl. No. 12/764,870. |
US Office Action, dated Aug. 28, 2002, issued in U.S. Appl. No. 09/975,612. |
US Office Action, dated Dec. 19, 2002, issued in U.S. Appl. No. 10/121,949. |
US Notice of Allowance, dated Jun. 3, 2003, issued in U.S. Appl. No. 10/121,949. |
US Office Action, dated Jun. 15, 2004, issued in U.S. Appl. No. 10/289,237. |
US Notice of Allowance, dated Sep. 3, 2004, issued in U.S. Appl. No. 10/289,237. |
US Office Action, dated May 2, 2008, issued in U.S. Appl. No. 11/558,693. |
US Notice of Allowance, dated Nov. 24, 2008, issued in U.S. Appl. No. 11/558,693. |
US Office Action, dated May 7, 2012, issued in U.S. Appl. No. 12/391,719. |
US Final Office Action, dated Oct. 15, 2012, issued in U.S. Appl. No. 12/391,719. |
US Office Action, dated Jun. 26, 2008, issued in U.S. Appl. No. 11/473,618. |
US Final Office Action, dated Dec. 10, 2008, issued in U.S. Appl. No. 11/473,618. |
US Office Action, dated on Mar. 24, 2009, issued in U.S. Appl. No. 11/473,618. |
US Notice of Allowance, dated Sep. 4, 2009, issued in U.S. Appl. No. 11/473,618. |
US Office Action, dated on May 26, 2009, issued in U.S. Appl. No. 11/564,222. |
US Office Action, dated May 5, 2009, issued in U.S. Appl. No. 11/588,586. |
US Final Office Action, dated Nov. 4, 2009, issued in U.S. Appl. No. 11/588,586. |
US Notice of Allowance, dated Mar. 24, 2010, issued in U.S. Appl. No. 11/588,586. |
US Office Action, dated Aug. 9, 2011, issued in U.S. Appl. No. 11/977,355. |
US Final Office Action, dated Dec. 15, 2011, issued in U.S. Appl. No. 11/977,355. |
US Office Action, dated Nov. 12, 2010, issued in U.S. Appl. No. 11/830,777. |
US Final Office Action, dated Apr. 15, 2011, issued in U.S. Appl. No. 11/830,777. |
US Notice of Allowance, dated Jun. 27, 2011, issued in U.S. Appl. No. 11/830,777. |
US Office Action, dated Nov. 14, 2008, issued in U.S. Appl. No. 11/701,984. |
US Office Action, dated on Feb. 23, 2009, issued in U.S. Appl. No. 11/701,984. |
US Final Office Action, dated Jun. 17, 2009, issued in U.S. Appl. No. 11/701,984. |
US Notice of Allowance, dated Nov. 9, 2009, issued in U.S. Appl. No. 11/701,984. |
US Office Action, dated Dec. 19, 2011, issued in U.S. Appl. No. 12/699,738. |
US Final Office Action, dated Apr. 9, 2012, issued in U.S. Appl. No. 12/699,738. |
US Notice of Allowance, dated Jun. 25, 2012, issued in U.S. Appl. No. 12/699,738. |
US Supplemental Notice of Allowability, dated Jul. 20, 2012, issued in U.S. Appl. No. 12/699,738. |
US Office Action, dated Mar. 2, 2010, issued in U.S. Appl. No. 11/807,182. |
US Final Office Action, dated Sep. 14, 2010, issued in U.S. Appl. No. 11/807,182. |
US Notice of Allowance, dated Nov. 30, 2010, issued in U.S. Appl. No. 11/807,182. |
US Notice of Allowance, dated Jan. 9, 2013, issued in U.S. Appl. No. 13/033,349. |
US Office Action, dated May 12, 2010, issued in U.S. Appl. No. 11/807,183. |
US Notice of Allowance, dated Nov. 1, 2010, issued in U.S. Appl. No. 11/807,183. |
US Office Action, dated Mar. 5, 2010, issued in U.S. Appl. No. 11/807,178. |
US Notice of Allowance dated Sep. 27, 2010, issued in U.S. Appl. No. 11/807,178. |
US Office Action, dated Feb. 4, 2010, issued in U.S. Appl. No. 11/807,179. |
US Notice of Allowance, dated Jul. 27, 2010, issued in U.S. Appl. No. 11/807,179. |
US Office Action, dated Aug. 9, 2011, issued in U.S. Appl. No. 12/467,200. |
US Final Office Action, dated Feb. 28, 2012, issued in U.S. Appl. No. 12/467,200. |
US Notice of Allowance, dated Jul. 6, 2012, issued in U.S. Appl. No. 12/467,200. |
US Office Action, dated Apr. 5, 2013, issued in U.S. Appl. No. 12/910,623. |
US Office Action, dated on Mar. 6, 2009, issued in U.S. Appl. No. 11/903,487. |
US Notice of Allowance, dated Sep. 18, 2009, issued in U.S. Appl. No. 11/903,487. |
US Office Action, dated Oct. 6, 2009, issued in U.S. Appl. No. 12/154,984. |
US Final Office Action, dated Apr. 15, 2010, issued in U.S. Appl. No. 12/154,984. |
US Office Action, dated Jul. 23, 2009, issued in U.S. Appl. No. 12/122,118. |
US Final Office Action, dated Mar. 11, 2010, issued in U.S. Appl. No. 12/122,118. |
US Office Action, dated Jul. 30, 2010, issued in U.S. Appl. No. 12/122,118. |
US Final Office Action, dated Nov. 15, 2010, issued in U.S. Appl. No. 12/122,118. |
US Notice of Allowance, dated May 25, 2011, issued in U.S. Appl. No. 12/122,118. |
Arcot et al. (Nov. 1, 1994) “Intermetallic Formation in Copper/Magnesium Thin Films—kinetics, Nucleation and Growth, and Effect of Interfacial Oxygen,” J. Appl. Phys. 76(9), pp. 5161-5170. |
Ashanti et al. (Jul./Aug. 2000) “A New Hollow-Cathode Magnetron Source for 0.10.mu.m Copper Applications”, Journal of Vacuum Science and Technology, A18(4) p. 1546. |
Braeckelmann et al. (Feb. 2000) “Integration and Reliability of Copper Magnesium Alloys for Multilevel Interconnects,” IEEE, pp. 236-238. |
Chen et al. (Jan./Feb. 1999) “Low Temperature Plasma-Assisted Chemical Vapor Deposition of Tantalum Nitride form Tantalum Pentabromide for Copper Metallization,” J. Vac. Sci. Technol., B 17(1), pp. 182-185. |
Cheng et al. (Mar./Apr. 1995) “Directional Deposition of Cu into Semiconductor Trench Structures Using Ionized Magnetron Sputtering,” J. Vac. Sci. Technol., B.13(2), pp. 203-208. |
Cho et al. (1999) “Factors Affecting Passivation and Resistivity of Cu(Mg) Alloy Film,” Materials Research Society Symposium Proc. vol. 564, pp. 353-358. |
Cho et al. (Dec. 1998) “Remote Plasma-Assisted Metal Organic Chemical Vapor Deposition of Tantalum Nitride Thin Films with Different Radicals,” Jpn. J. Appl. Phys., vol. 37. |
Cohen et al. (Jun. 16-Jun.18, 1998) “Reactive Preclean Technology for Nonphysical Copper Oxide Reduction for Advanced CU Interconnect”, VMIC Conference, pp. 91 and 93. |
D'Couto et al. (2001) “In situ physical vapor deposition of ionized Ti and TiN thin films using hollow cathode magnetron plasma source,”J. Vac.Sci.Technol. B. 19(1), pp. 244-249. |
Ding et al. (1993) “Observation of Reduced Oxidation Rates for Plasma-Assisted CVD Copper Films”, Mat. Res. Soc. Symp. Proc., vol. 309, pp. 445-460. |
Ding et al. (Apr. 1994) “Effects of the addition of small amounts of A1 to copper: Corrosion, resistivity, adhesion, morphology, and diffusion,” J. Appl. Phys. 75(7):3627-3631. |
Endle et al. (May/Jun. 1998) “X-Ray Photoelectron Spectroscopy Study on TiN Films Produced with Tetrakis (dimethylamido)Titanium and Selected N-Containing Precusors on SiO.sub.2,” J. Vac. Sci. Technol., A 16(3), pp. 1262-1267. |
Font et al. (Oct. 1999) “Scaling of Hollow Cathode Magnetrons for Metal Deposition,” University of Illinois (20 pages). |
Green et al. (Dec. 1997) “Determination of Flux Ionization Fraction Using a Quartz Crystal Microbalance and a Gridded Energy Analyzer in an Ionized Magnetron Sputtering System,” Rev. Sci. Instrum., 68 (12), pp. 4555-4560. |
Han et al. (May 1998) “Barrier Metal Properties of Amorphous Tantalum Nitride Thin Films Between Platinum and Silicon Deposited Using Remote Plasma Metal Organic Chemical Vapor Method,” Jpn. J. Appl. Phys., vol. 37 (1998), Pt. 1, No. 5A, pp. 2646-2651. |
Hayden et al. (1999) “Helion Plasma Source for Ionized Physical Vapor Deposition,” 1999, Surface and Coatings Technology, 120-121, pp. 401-404. |
Hayden et al. (Mar./Apr. 1998) “Characterization of Magnetron-Sputtered Partially Ionized Aluminum Deposition,” J. Vac. Sci. Technol., A 16(2), pp. 624-627. |
Hoekstra et al. (Jul./Aug. 1998) “Microtenching resulting from specular reflection during chlorine etching of silicon,” J.Vac. Sci. Technol. B 16(4), pp. 2102-2104. |
Jian Li and J. W. Mayer and E. G. Colgan. (Sep. 1, 1991) “Oxidation and Protection in Copper and Copper Alloy Thin Films”, J. Appl. Phys. 70 (5), pp. 2820-2827. |
Klawuhn et al. (Jul./Aug. 2000) “Ionized Physical-vapor deposition Using a Hollow-Cathode Magnetron Source for Advanced Metallization”, J. Vac, Sci, Technol. A18(4), pp. 1546-1549. |
Lane et al. (Jan./Feb. 2000) “Feature evolution during plasma etching. II. Polycrystalline silicone etching,” J.Vac. Sci. Technol. A 18(1), pp. 188-196. |
Lee et al. (1996) “The Failure Mechanism of MOCVD TiN Diffusion Barrier at High Temperature,” Mat. Res. Soc. Symp. Proc., vol. 324, pp. 279-284. |
Lu et al. (Jun. 2000) “An Integrated Plasma Equipment-feature Scale Model for Ionized Metal Physical Vapor Deposition”, University of Illinois (16 pages). |
Lucovsky et al. (Feb. 1990) “Formation of Thin Fims by Remote Plasma Enhanced Chemical Vapor Deposition (Remote PECVD),” in Handbook of Plasma Processing Technology, eds. Rossnagel, Cuomo and Westwood, Noyes Publications, pp. 387-408. |
M. Zinke-Allmang. (1999) Thin Solid Films 346, 1-68, “Phase Separation on Solid Surfaces: Nucleation, Coarsening and Coalescence Kinetics”. |
Murarka et al. (1995) “Copper Metallization for ULSI and Beyond,” Critical Reviews In Solid State and Materials Sciences, pp. 87-124. |
Musher et al. (Feb. 1996) Atmospheric Pressure Chemical Vapor Deposition of Titanium Nitride from Tetrakis (diethylamido) Titanium and Ammonia, J. Electochem. Soc., vol. 143, No. 2, pp. 736-744. |
Peijun Ding, et al. (Jun. 10-12, 1997) “Copper Barrier, Seed Layer and Planarization Technologies,” VMIC Conference, pp. 87-92. |
Peng et al. (Jul./Aug. 1998) “Structural and Electrical Properties of Chemical Vapor Deposition Tungsten Overgrowth on Physical Vapor Deposited and Metalorganic Chemical Vapor Deposited TiNAdhesion Layers,” J. Vac. Sci. Technol., B 16(4), pp. 2013-2018. |
Reif, Rafael. (Feb. 1990) Plasma Enhanced Chemical Vapor Deposition of Thin Films for Microelectronics, in Handbook of Plasma Processing Technology, eds: Rossnagel, Cuomo and Westwood, Noyes Publications, pp. 260-284. |
Saito et al. (2002) “Copper wires for high speed logic LSI prepared by low pressure long throw sputtering method,” Materials Transactions, vol. 43, No. 7, pp. 1599-1604. |
Schiller, S. et al., “High-rate vapor deposition and large systems for coating processes,” J.Vac.Sci.Technol., vol. 5, Iss. 4, Jul.-Aug. 1987, pp. 2239-2245. |
Schumacher Products, TDEAT (Tetrakis-diethylamino Titanium), Electronic Grade, www.schumacher.com/tdeat.html, printed Jun. 5, 2001, 1 page. |
Sun et al. (May 1998) Suppression of Cobalt Silicide Agglomeration Using Nitrogen (N2+) Implantation, IEEE Electron Device Letters, vol. 19, No. 5, pp. 163-166. |
T. Suwwan de Felipe et al. (Nov./Dec. 1997) “Bias-temperature stability of the Cu(Mg)/SiO.sub.2/p-Si metal-oxide-semiconductor capacitors,” J. Vac. Sci. Technol. B 15(6), pp. 1987-1986. |
Tarek Suwwan de Felipe, et al. (Jun. 1999) “Electrical Stability and Microstructual Evolution in Thin Films of High Conductivity Copper Alloys,” IEEE, pp. 293-295. |
Thornburg, D. D. et al., “Temperature Changes in Thin Films during Growth by Physical Vapor Deposition. II. Experimental,” J.Appl.Phys., vol. 42, Iss. 10, Sep. 1971, pp. 4071-4079. |
Truong, C.M.; Chen, P.J.; Corneille, J.S.; Oh, W.S. and Goodman, D.W. (1995) “Low-Pressure Deposition of TiN Thin Films from a Tetrakis (diethylamido) Titanium Precursor,” J. Phys. Chem, 99, pp. 8831-8842. |
Tsai et al. (May 1996) “Comparison of the Diffusion Barrier Properties of Chemical-Vapor-Deposited TaN and Sputtered TaN Between Cu and Si,” J. Appl. Phys., 79 (9), pp. 6932-6938. |
Vyvoda et al. (Mar./Apr. 2000) “Role of sidewall scattering in featuring profile evolution during CI2 and HBr plasma etching of silicon,” J.Vac.Sci.Technol. B 18(2), pp. 820-833. |
US Office Action dated Sep. 19, 2013 in U.S. Appl. No. 13/904,464. |
US Notice of Allowance dated Jan. 10, 2014 in U.S. Appl. No. 13/904,464. |
US Advisory Action, dated Dec. 28, 2012, issued in U.S. Appl. No. 12/391,719. |
US Office Action, dated Mar. 4, 2014, issued in U.S. Appl. No. 12/391,719. |
US Final Office Action, dated Oct. 25, 2013, issued in U.S. Appl. No. 12/910,623. |
US Notice of Allowance, dated Mar. 3, 2014, issued in U.S. Appl. No. 12/910,623. |
Snodgrass et al. (Feb. 2002) “A Statistical Analysis of Copper Bottom Coverage of High-Aspect-Ratio Features Using Ionized Physical Vapor Deposition,” IEEE Transactions on Semiconductor Manufacturing, 15(1):30-38. |
Notice of Entry of Judgment Accompanied by Opinion dated Nov. 14, 2014, Rozbicki v. Chiang, U.S. Court of Appeals for the Federal Circuit, Case No. 2014-1041. |
US Notice of Allowance, dated Jun. 17, 2014, issued in U.S. Appl. No. 12/391,719. |
Number | Date | Country | |
---|---|---|---|
60275803 | Mar 2001 | US | |
60379874 | May 2002 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 13904464 | May 2013 | US |
Child | 14171590 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 12764870 | Apr 2010 | US |
Child | 13904464 | US | |
Parent | 11714465 | Mar 2007 | US |
Child | 12764870 | US | |
Parent | 10804353 | Mar 2004 | US |
Child | 11714465 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 10412562 | Apr 2003 | US |
Child | 10804353 | US | |
Parent | 09965472 | Sep 2001 | US |
Child | 10412562 | US |