METHOD OF ELIMINATING SURFACE STRESS OF SILICON WAFER

Abstract

This invention provides a method for eliminating the surface stress of a silicon wafer comprising forming one or more anti-stress groove(s) on the surface of the silicon wafer. These anti-stress grooves can reduce or eliminate the surface stress of silicon wafer effectively to avoid the formation of slip lines and dislocation arrangements, which may induce the p-n junction to conduct or the leakage current to increase. The process is highly efficient and low in cost. It is simple to manage and does not require additional equipment beyond that already used for processing of silicon wafers.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Below, the invention is explained in more detail with reference to accompanying drawings, in which:

FIG. 1 illustrates slip lines on a silicon wafer surface;

FIG. 2 illustrates the distribution of anti-stress grooves;

FIG. 3 illustrates the effect of a closed anti-stress groove on the formation of slip lines; and

FIG. 4 illustrates the effect of an open anti-stress groove on the formation of slip lines.

DETAILED DESCRIPTION OF THE INVENTION

A method of eliminating surface stress in a silicon wafer comprises scoring an anti-damage circular groove on the silicon surface of the wafer.

The number of grooves is related to the diameter of the silicon wafer and can be expressed by the following formula:

N=(kφ−n)/m

wherein k (in mm⁻), n, m are constants and φ is the radius of silicon wafer (in mm).

The radius of the outermost groove is no closer than 2-3 mm from the edge of wafer, and at most 0.5-1 mm from the wafer flat. The depth of the anti-stress grooves is about 2-10% of the silicon wafer thickness. The groove angle is about 10 to 50 degrees. The pressure used to create the grooves is 2-5 kg-force per square meter.

EXAMPLES

Example 1

The Effect of a Closed Anti-Stress Groove on the Formation of Slip Lines

A silicon wafer with radius φ=35 mm and resistivity of 2-3×10³Ω·cm was used in the experiment. The wafer was grinded and epitaxial growth was completed at 1200° C. Thereafter, a closed anti-stress groove was scored with a diamond blade at 3 mm from the edge of wafer. No slip lines were observed.

Example 2

The Effect of two Closed Anti-Stress Grooves on the Formation of Slip Lines

Two uniform wafers, A and B, with radius φ=50 mm and resistivity 2-3×10³Ω·cm were studied. Wafer A was scored with one groove at 3 mm from the edge of wafer, while wafer B was scored with two grooves: one at 3 mm from the edge of the wafer and the other at 12.5 mm from the center of the wafer. Thereafter, the wafers were grinded and epitaxial growth was completed at 1200° C. On wafer A, no slip lines were observed within 20 mm from edge, but there was a shallow slip line close to the wafer centre. On wafer B, no slip lines were observed.

Example 3

The Effect of Several Closed Anti-Stress Grooves on the Formation of Slip Lines

Two uniform wafers, A and B, with radius φ=100 mm and resistivity 2-3×10³Ω·cm were studied. Wafer A was scored with two grooves: one at 3 mm from the edge of wafer and the other at 37.5 mm from the center. Wafer B was scored with four grooves: one at 3 mm from the edge of wafer, and the other ones at 2.5 mm, 25 mm and 37.5 mm from the center, respectively. Thereafter, the wafers were grinded and epitaxial growth was completed at 1200° C. On wafer A, no slip lines were observed within 60 mm from edge, but there was a shallow slip line close to the wafer centre. On wafer B, no slip lines were observed.

This invention is not to be limited to the specific embodiments disclosed herein and modifications for various applications and other embodiments are intended to be included within the scope of the appended claims. While this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.

All publications and patent applications mentioned in this specification are indicative of the level of skill of those skilled in the art to which this invention pertains. All publications and patent applications mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication or patent application mentioned in this specification was specifically and individually indicated to be incorporated by reference.

Claims

1. A method of eliminating surface stress of silicon wafer comprising forming one or more anti-stress groove(s) on the silicon surface of the silicon wafer.

2. The method of claim 1, wherein said anti-stress grove(s) are formed after the silicon wafer is processed by slicing and/or grinding.

3. The method of claim 1, wherein the anti-stress groove(s) that is closest to wafer's edge is disposed not closer than 2-3 mm from the wafer's edge and not closer than 0.5-1 mm from wafer's flat.

4. The method of claim 1, wherein: Ri=k*i, i is a groove number counting from the centre of the wafer to the edge of the wafer starting with 1;Ri is the radius of the ith groove (in mm); andk is a constant in the range from 10 to 13 mm.

5. The method of claim 1, wherein said anti-stress grove(s) have a depth of 2-10% with respect to a thickness of the silicon wafer.

6. The method of claim 1, wherein said anti-stress grove(s) are shaped like a trench, the sides of said trench forming a 10-50 degrees angle with the normal to the silicon wafer.

7. The method of claim 1, wherein said anti-stress grove(s) are formed by cutting the silicon wafer with a diamond blade.

8. The method of claim 7, wherein said diamond blade is applied to the surface of the silicon wafer with a pressure of 2-5 kg-force per square meter.