Claims
- 1. A method of fabricating a bipolar transistor comprising the steps of:
- 1) forming a multilayer structure by sequentially stacking on a semi-insulating substrate, a collector contact layer, a collector layer, a base layer, and an emitter layer in this order;
- 2) forming a first mask on a part of the multilayer structure;
- 3) changing the collector contact layer and the collector layer to be a first semi-insulative region by a deep ion-implantation at portions except for portions below the first mask so that the portions of the collector contact layer and the collector layer below the first mask become a collector contact region and a collector region, respectively;
- 4) forming a second mask on a part of the multilayer structure to partly overlap a part of the first mask;
- 5) removing the first mask except for the part overlapped with the second mask;
- 6) changing the base layer to be second semi-insulative region by a shallow ion-implantation at a portion except for a portion below the second mask so that the portion of the base layer below the second mask becomes a base region having an extrinsic base region formed on the first semi-insulative region;
- 7) removing the second mask so that the part of the first mask which was overlapped with the second mask remains as a third mask;
- 8) etching off the emitter layer at a portion except for a portion below the third mask so that the portion of the emitter layer below the third mask remains as an emitter region; and
- 9) removing the third mask.
- 2. The method of claim 1, wherein the bandgap of a material of the emitter layer described in the step 1) is wider than that of a material of the base layer.
- 3. The method of claim 1, further comprising, between the step 3) and step 4), an additional step of implanting ions into the extrinsic base region upon the first semi-insulative region such that the resistance of said extrinsic base region is reduced.
- 4. A method of fabricating a bipolar transistor comprising the steps of:
- 1) forming a multilayer structure by sequentially stacking on a semi-insulating substrate, an emitter contact layer, an emitter layer, a base layer, and a collector layer in this order;
- 2) forming a first mask on a part of the multilayer structure;
- 3) changing the emitter contact layer and the emitter layer to be a first semi-insulative region by a deep ion-implantation at portions except for portions below the first mask so that the portions of the emitter contact layer and the emitter layer below the first mask become an emitter contact region and an emitter region, respectively;
- 4) forming a second mask on a part of the multilayer structure to partly overlap a part of the first mask;
- 5) removing the first mask except for the part overlapped with the second mask;
- 6) changing the base layer to be a second semi-insulative region by a shallow ion-implantation at a portion except for a portion below the second mask so that the portion of the base layer below the second mask becomes a base region having an extrinsic base region formed on the first semi-insulative region;
- 7) removing the second mask so that the part of the first mask which was overlapped with the second mask remains as a third mask;
- 8) etching off the collector layer at a portion except for a portion below the third mask so that the portion of the collector layer below the third mask remains as a collector region; and
- 9) removing the third mask.
- 5. The method of claim 4, wherein the bandgap of a material of the emitter layer described in the step 1) is wider than that of a material of the base layer.
- 6. The method of claim 4, further comprising, between the step 3) and the step 4), an additional step of implanting ions into the extrinsic base region upon the first semi-insulative region such that the resistance of said extrinsic base region is reduced.
Priority Claims (2)
Number |
Date |
Country |
Kind |
62-186176 |
Jul 1987 |
JPX |
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62-186181 |
Jul 1987 |
JPX |
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Parent Case Info
This application is a division of now abandoned application Ser. No. 07/224,009 filed on Jul. 25, 1988, now abandoned.
US Referenced Citations (3)
Foreign Referenced Citations (4)
Number |
Date |
Country |
60-7771 |
Jan 1985 |
JPX |
60-95966 |
May 1985 |
JPX |
62-81759 |
Apr 1987 |
JPX |
62-117369 |
May 1987 |
JPX |
Non-Patent Literature Citations (2)
Entry |
AlGaAs/GaAs Heterojunction Bipolar Transistors with Small Size Fabricated by a Multiple Self-Alignment Process Using One Mask IEEE Transactions on Electron Devices, vol. ED-34 No. 12, Dec. 1987. |
GaAs/(Ga, Al) As Heterojunction Bipolar Transistors with Buried Oxygen-Implanted Isolation Layers IEEE Electron Device Letters, vol. EDL-5, No. 8, Aug. 1984. |
Divisions (1)
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Number |
Date |
Country |
Parent |
424009 |
Jul 1988 |
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