Patent Application
20090115027
The present invention relates to a method of fabricating an integrated circuit.
One driving motivator in commercial memory cells and architecture is the desire to pack more memory capability into smaller integrated circuits. This goal necessarily involves competing trade-offs in cost, circuit complexity, power dissipation, yield, performance, and the like. Trench capacitors are known in the art as an architecture whereby the overall size (in terms of surface area or chip “real estate”) of the memory cell is reduced. The size reduction is accomplished by forming the capacitor of the memory cell in a trench.
As is known in the art, a typical DRAM cell includes a capacitor upon which is stored a charge (or no charge depending upon the cell's state) and a pass transistor, which is used to charge the capacitor during writing and in the read process to pass the charge on the capacitor to a sense amplifier.
In most recent manufacturing, planar transistors are used for the pass transistors. The associated capacitor can be formed in a deep trench. Accordingly, deep trench memory cells represent one approach to meet the challenges of providing high capacitance structures in small areas.
In the accompanying drawings:
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
As depicted in the enlarged view of an upper section 21 of the trenches 2, they comprise a number of defects 3 which have developed during the etching of the trenches. The defects 3 are formed in a substrate portion 25 adjacent to the trenches and comprise, e.g., cavity like defects 31 having irregular contours as well as longitudinal defects 32 (worm holes).
Due to the CH4 precursor a material layer in the form of a passivation layer was generated at a substrate portion (sidewall) adjacent to an etched region in the form of an opening in the substrate (upper part of the trenches 2) during the etching, the passivation layer formed from a Si/C/O (silicon/carbon/oxide; SixCyOz) composition. The Si/C/O containing passivation layer provided a protection of the trench sidewalls during the trench etching such that the number and the size of sidewall defects were reduced. This is depicted in the enlarged upper section 21 of the deep trench structures 2 showing essentially defect free trenches.
It is noted that the passivation layer can be formed as a separate layer on the sidewall of the etched part of the trenches. In another embodiment the passivation layer is formed integrally with the sidewall by modifying the substrate portion adjacent to the etched part of the trenches, e.g., by incorporating material particles into the substrate portion.
Although CH4 has been used for generating the deep trench structures 2 of
In another embodiment, a precursor is used that generates a silicon/metal composition on the sidewall of the etched portion of a structure. In this case, the precursor can comprise titanium, e.g., in the form of TiCl4, such that a passivation layer containing a silicon/titanium composition is produced. In another example the precursor comprises tantalum such as a precursor comprising tantalum chloride.
Also, a combination of different precursors is possible such that a passivation layer comprising both a Si/C/O and a Si/metal composition is generated. For example, different precursors are used successively such that a first sidewall portion comprises Si/C/O and a second sidewall portion comprises a Si/metal composition.
If CH4 is used as a precursor, in one embodiment of the invention, the plasma conditions are chosen such that most or essentially the entire CH4 precursor is decomposed. In this case, the plasma conditions include, e.g., an excitation frequency in the range of approximately 40 MHz to 100 MHz, in particular 60 MHz, and an excitation power in the range of approximately 800 to 1200 Watts, in particular, 1000 Watts in particular.
In a further example, the concentration of the precursor relative to the etching gas and the plasma conditions are chosen to generate a passivation layer of the predetermined stoichiometry, i.e., the composition of the Si/C/O passivation layer can be adapted (and, e.g., adapted to the used etching gas) by the plasma conditions and the precursor concentration relative to the etching gas. The precursor can in principle be combined with all conventional etching gases.
In an embodiment of the inventive method, the precursor is added to the etching gas during the complete etching process. In another example, the precursor is added during one or more distinct periods of the etching process, only. For example, the precursor is added at the beginning and during an end phase of the etching process, while the etching process also comprises etching steps without the precursor.
It is noted that although
As illustrated in
