Claims
- 1. In a method of fabricating antifuses in an integrated circuit including the step of depositing a layer of amorphous silicon, an improvement comprising
- depositing said amorphous silicon layer in a process chamber having a low-pressure atmosphere with essentially no nitrogen, said atmosphere lower than ambient;
- removing said atmosphere from said chamber at a rate of no more than 2 millitorr per minute;
- whereby the avoidance of silicon nitride deposition in said amorphous silicon layer is enhanced.
- 2. The improvement of claim 1 further comprising
- pumping down said chamber to a base pressure and purging said chamber with a gas repeatedly prior to said amorphous silicon depositing step.
- 3. The improvement of claim 2 wherein said base pressure is no more than 20 millitorr and said gas is from the group of nitrogen and argon.
- 4. In a method of fabricating antifuses in an integrated circuit including the step of depositing a layer of amorphous silicon, an improvement comprising
- depositing said amorphous silicon in a process chamber by plasma-enhanced chemical vapor deposition at a temperature in the range of 300.degree.-400.degree. C.; and
- running a mixture of argon and 5-10% silane through said process chamber at a flow rate of 4000 sccm for argon and at a flow rate of 200-400 sccm for silane.
- 5. The method of claim 4 wherein said process chamber of said depositing step has a low-pressure atmosphere with essentially no nitrogen, said atmosphere lower than ambient; and further including the step of removing said atmosphere from said chamber at a rate of no more than 2 millitorr per minute;
- whereby the avoidance of silicon nitride deposition in said amorphous silicon layer is enhanced.
- 6. In a method of fabricating antifuses in an integrated circuit including the step of depositing a layer of amorphous silicon, an improvement comprising
- depositing said amorphous silicon in a process chamber by plasma-enhanced chemical vapor deposition at a temperature in the range of 300.degree.-400.degree. C. and at a pressure in the range of 2-6 Torr.
- 7. The method of claim 6 wherein said process chamber has an atmosphere with essentially no nitrogen, and further including the step of removing said atmosphere from said chamber at a rate of no more than 2 millitorr per minute;
- whereby the avoidance of silicon nitride deposition in said amorphous silicon layer is enhanced.
Parent Case Info
This application is a Rule 60 continuation application of Ser. No. 08/158,134, filed Nov. 24, 1993, now U.S. Pat. No. 5,527,745; which is a Rule 60 Divisional of Ser. No. 07/782,837, filed Oct. 24, 1991, now U.S. Pat. No. 5,322,812; which is a continuation-in-part of Ser. No. 07/672,501, filed Mar. 20, 1991, now abandoned.
US Referenced Citations (5)
Foreign Referenced Citations (1)
Number |
Date |
Country |
2556275 |
Jul 1976 |
DEX |
Non-Patent Literature Citations (1)
Entry |
Sze, VLSI Technology, 1988, McGraw-Hill pp. 377, 380-382. |
Divisions (1)
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Number |
Date |
Country |
Parent |
782837 |
Oct 1991 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
158134 |
Nov 1993 |
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Continuation in Parts (1)
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Number |
Date |
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Parent |
672501 |
Mar 1991 |
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