Claims
- 1. A process of fabricating a memory transistor, said process comprising the steps of:
- providing a semiconductor substrate:
- forming a pair of source/drain regions at a surface of said substrate, said source/drain regions being separated by a channel region;
- forming a gate oxide layer over said source/drain regions and said channel region;
- etching said gate oxide layer to expose a portion of said surface of said substrate, said portion comprising a tunnel oxide region, said tunnel oxide region overlying one of said source/drain regions;
- growing a tunnel oxide layer in said tunnel oxide region;
- depositing a first conductive layer over said gate oxide layer and said tunnel oxide layer;
- depositing an insulating layer over said first conductive layer;
- forming a first mask over said insulating layer;
- etching said insulating layer in areas thereof not covered by said first mask;
- etching said first conductive layer to form a floating gate, said floating gate covering said tunnel oxide region and having a peripheral edge which surrounds said tunnel oxide region;
- depositing a second conductive layer over said insulating layer;
- forming a second mask over said second conductive layer; and
- etching said second conductive layer in areas thereof not covered by said second mask to form a control gate, said control gate being sized and positioned such that a peripheral region of said floating gate extends laterally outward beyond said control gate along an entire length of said peripheral edge of said control gate.
- 2. The process of claim 1 including the further step of forming a MOSFET in said substrate, including the step of forming a second gate oxide layer for said MOSFET after the formation of said floating gate, said second gate oxide layer growing on a sidewall of said floating gate.
- 3. The process of claim 1 wherein said step of etching said first conductive layer to form a floating gate produces a floating gate having a sloped sidewall.
- 4. The process of claim 1 comprising the further step of etching said gate oxide layer after said floating gate is formed, using a two-step etch including a dry anisotropic etch followed by a wet etch.
Parent Case Info
This application is a division of application Ser. No. 08/298,239, filed Aug. 30, 1994, now abandoned.
US Referenced Citations (12)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0256993 |
Feb 1988 |
EPX |
Divisions (1)
|
Number |
Date |
Country |
Parent |
298239 |
Aug 1994 |
|