BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIGS. 1A through 1F are schematic cross-sectional views showing the steps for fabricating a non-volatile memory according to the preferred embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
FIGS. 1A through 1F are schematic cross-sectional views showing the steps for fabricating a non-volatile memory according to the preferred embodiment of the present invention.
As shown in FIG. 1A, a tunneling oxide layer 102 is formed on a substrate 100. In general, a thermal oxidation process is performed to form the tunneling oxide layer 102. The substrate 100 is a silicon substrate and the tunneling oxide layer is fabricated using silicon oxide, for example.
As shown in FIG. 1B, a surface nitridation process 103 is performed to nitridize the upper surface of the tunneling oxide layer 102 into a nitridized surface 104 such as a oxy-nitride layer or a nitridized layer. The surface nitridation process 103 can be a thermal nitridation process or a plasma nitridation process. Because the thermal nitridation process can prevent so many nitrogen atoms from penetrating into the tunneling oxide layer 102 that affect the electrical properties (for example, inducing a larger leakage current) of the memory, it is selected as the preferred embodiment.
Again, as shown in FIG. 1B, when a thermal nitridation process is used as the surface nitridation process 103, the processing temperature is in a range of about 650° C. to 1000° C. and the nitridation period is in a range of about 10 minutes to 90 minutes, for example.
As shown in FIG. 1C, nano-dots 106 are formed on the upper surface 104 of the nitridized tunneling oxide layer 102. In this step, the nano-dots are fabricated using, for example, silicon (Si), germanium (Ge) or other material capable of forming nano-dots through grain growth. Because the surface 104 of the nitridized tunneling oxide layer 102 has a large number of dangling bonds, nanocrystals grow densely on the aforementioned surface 104 to produce a high-density nano-dot structure. The density of the nano-dots 106 is, for example, greater than 5×1011 dots/cm2, but preferably greater than 1×1012 dots/cm2. In the present embodiment, the nano-dots 106 have a particle size smaller than 5 nanometers (nm), for example.
The process up to this stage constitutes a method for fabricating the charge storage layer of a memory. Because the fabrication of the charge storage layer is one key aspect of improving the properties of the non-volatile memory in the present invention, it needs to be specified. Furthermore, a nitridation process on the surface of the tunneling oxide layer is performed to produce more dangling bonds so that high-density nanocrystals (nano-dots) are grown thereon. In addition, the nitridation process will not compromise the uniformity of the surface of the tunneling oxide layer. Moreover, compared with a deposition process, the nitridation process is capable of forming a thinner nitride layer or oxy-nitride layer on the tunneling oxide layer. As a result, the method not only increases the charge storage density, but also reduces the leakage current and operation voltage because it provides a thin tunneling oxide layer having a uniform nitridized upper surface with dangling bonds.
FIG. 1D is a sectional magnified view of the D portion of FIG. 1C. As shown in FIG. 1D, the surface of the nano-dots 106 is nitridized to form a thin protective layer 108. The process of forming the protective layer 108 on the surface of the nano-dots 106 includes exposing the nano-dots 106 in a nitrogen-containing gas, such as nitrogen gas, and heating to a temperature of about 300° C. to 650° C., for example. Typically, the protective layer 108 is fabricated using silicon nitride. One principal function of the protective layer 108 is to prevent the surface of nano-dots 106 from oxidation.
As shown in FIG. 1E, an oxide layer 110 is formed on the surface of the tunneling oxide layer 102 to cover the nano-dots 106. The method of forming the oxide layer 110 includes performing a chemical vapor deposition process, for example.
As shown in FIG. 1F, a conductive layer 112 is formed on the oxide layer 110 to serve as a control gate for the non-volatile memory. The conductive layer 112 can be a doped polysilicon layer, for example. Afterwards, other steps, such as doping/ion implantation processes, are subsequently carried out to complete the fabrication of a memory device.
In summary, the fabrication of nano-crystal non-volatile memory in the present invention involves growing nano-dots on the surface of a nitridized tunneling oxide layer, thereby eliminating the need to perform a conventional surface treatment of the tunneling oxide layer with chemicals before actually growing the nano-dots. Furthermore, the present invention may also reduce the possibility of high leakage current and operation voltage since the nano-dots are not grown directly on a deposited nitride layer according to the invention. Thus, compared with the nano-dots grown on a conventional oxide layer, the present invention not only increases the distribution density of nano-dots, but also decreases the particle size of nano-dots. Therefore, the threshold voltage shift is increased so that the memory window of the memory is effectively increased.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Patent Application
20070249121
