Patent Application
20160027521
One or more aspects of embodiments according to the present invention relate to a method of flash channel calibration with multiple LUTs for adaptive multiple-read.
With the shrink of lithographic geometry for the NAND flash, the area of the memory cells get smaller, the number of electrons that can be used in storage drops, and it becomes more difficult to assure accurate information storage. Meanwhile high-capacity NAND flash memory can achieve high density storage by using multi-level cells (2 bits/cell for MLC or 3 bits/cell for TLC in the market) to store more than one bit per cell. Four and eight levels are currently in use, and the number of levels will increase further to provide more storage capability. The increasing number of levels (and smaller distance between levels) means that the lower signal-to-noise ratio of the read channel makes a stronger error-correction code (ECC) necessary. Reductions in feature size make inter-cell interference more likely.
All the above two factors increase the raw bit error rate (RBER), making powerful error correction coding necessary, e.g. low density parity check (LDPC) codes.
LDPC codes are linear block codes defined by sparse parity check matrices, called H-matrix. By optimizing the degree distribution, it is well-known that LDPC codes can approach the capacity of an AWGN channel. Designing LDPC codes with low error-floors is crucial for flash memory since storage systems usually require un-correctable bit-error-rates lower than 10−16 for enterprise class SSD. LDPC decoders commonly use soft reliability information about the received bits, which can greatly improve performance. However, typically flash systems have provided only hard decision information to their decoders. Traditional codes, such as BCH codes can only correct a specified, fixed number of errors. Unlike these traditional codes, it is difficult to guarantee a specified number of correctable errors for LDPC codes. However the average bit-error rate performance can often outperform that of BCH codes in Gaussian noise.
Since the sense amplifier comparator in the NAND flash only provides one bit of information about the threshold voltage, ECC decoders for NAND flash controller have historically relied on hard decision bits from the sense-amp comparator. However, soft information can be obtained either by reading from the same sense amplifier comparator multiple times with different word line voltages or by equipping flash cells with multiple sense amplifier comparators (or higher precision ADC) on the bit line. However, the NAND flash with multiple comparators is not currently available in the market.
If a cell voltage is above reference voltage, it is considered as 0. Otherwise, it is considered as 1.
If multiple different reference voltages are applied, it will divide the whole voltage range into n+1 regions where n is the number of different reference voltages. In the above example, the 4 regions (region 3, 2, 1, 0) will be (−∞,VT−), (VT−, VT), (VT, VT+), (VT+, +∞) respectively.
If a cell with voltage in point A within region 3, it will be { 111 } with respect to voltage threshold {VT−, VT, VT+} in this example.
If a cell with voltage in point B within region 2, it will be {011} with respect to voltage threshold {VT−, VT, VT+} in this example.
If a cell with voltage in point C within region 1, it will be {001} with respect to voltage threshold {VT−, VT, VT+} in this example.
If a cell with voltage in point D within region 0, it will be {000} with respect to voltage threshold {VT−, VT, VT+} in this example.
By combining the outcomes of multiple-read, it is possible to generate the soft-decision information.
In the other hand, each Tread time is about 50 us for 2-bit/cell MLC, and above 100 us for 3-bit/cell TLC. The read of different threshold voltage of a certain flash page can only happen one at a time. Therefore it will save lots of time and power if we can make the multiple-read as less as possible. In other words, it will minimize the number of Tread and latency of M-RD. There is a need to enable this adaptive multiple-read for the NAND flash.
Aspects of embodiments of the present disclosure are directed toward a method of flash channel calibration with multiple LUTs for adaptive multiple-read.
These and other features and advantages of the present invention will be appreciated and understood with reference to the specification, claims and appended drawings wherein:
The detailed description set forth below in connection with the appended drawings is intended as a description of exemplary embodiments of a method of flash channel calibration with multiple LUTs for adaptive multiple-read provided in accordance with the present invention and is not intended to represent the only forms in which the present invention may be constructed or utilized. The description sets forth the features of the present invention in connection with the illustrated embodiments. It is to be understood, however, that the same or equivalent functions and structures may be accomplished by different embodiments that are also intended to be encompassed within the spirit and scope of the invention. As denoted elsewhere herein, like element numbers are intended to indicate like elements or features.
SoC—System on a Chip
SSD—Solid State Drive
SLC—Single-Level Cell
MLC—Multi-Level Cell
TLC—Thiple-Level Cell
ECC—Error Correction Codes
LDPC—Low Density Parity Codes
BER—Bit Error Rate
RBER—Raw Bit Error Rate
AWGN—Additive White Gaussian Noise
LUT—Look-Up-Table
M-RD—Multi-Read
CW—Code-Word
F/W—Firmware
LLR—Log-Likelihood Ratio
Embodiments of the invention are directed toward the method to obtain multiple sets of LUTs during NAND flash channel calibration for the adaptive multiple-read.
In order for ECC (or LDPC) decoder to perform adaptive multi-read scheme, it requires that the multiple sets of Look-Up-Tables (LUTs) are available. The LUTs are used to translate the pattern probability into soft-decision value. For example, as shown in the diagram 100 (
The LUT is used to translate the input bit pattern, for example {0 1 1}, into LLR soft-decision value for LDPC or other ECC method that is able to take soft-decision value. The LLR (Log Likelihood Ratio) is defined as
where P(0) is the possibility of “0” to be the transmitted bit, while P(1) is the possibility “1” to be the transmitted bit.
The LLR calibration is to find the probability of pattern appearance in logarithmic domain. It is based on bit flip count of decoded data versus the raw data. In calibration mode, multiple LUTs corresponding to different number of M-RD will be generated. It is the necessary procedure in order to support the adaptive multi-read (M-RD). The LLR value generated in calibration phase will be the LUTs used to translate input pattern to LLR soft-decision input for ECC decoder in the normal multiple-read decoding phase.
The multi-LUT NAND flash channel calibration system is presented in diagram 200 of
The calibration starts to read out data from a NAND flash page 220 with a pre-defined maximum multiple-read to intermediate buffer 210. It can be configured to read out only one code-word 280 or the whole page (multiple code-words). When performing multiple-read, different voltage setting will be applied. Then the intermediate buffer 210 sends the same code-word from reads with different threshold voltage to ECC sub-system 240. Those code-words are stored in the local memory 260 inside ECC sub-system. The LDPC decoder 250 will use all copies or some copies of code-word in 260, combine them together using LUT 255 into soft-decision input to 250. The content in LUT 255 has the default or less-accurate contents. Once LDPC decoder 250 is able to decoder a code word successfully, the statistics collector 251 will collect the 1 to 0 or 0 to 1 flip count by comparing the decoded data with all of the raw data. The multi-LUT generation 252 will generate or update multiple LUTs based on current setting. The new generated LUTs in 252 has more accurate channel information than the contents in LUT 255 during NAND flash channel calibration phase. Hence it can reduce the LDPC decoding later on when using updated channel LUTs. CPU sub-system 230 can read out the content in 252 and store it for future use or populate to 255.
Calibration unit requires a correctly decoded code-word using either one copy or multi-copies of raw data. It will need all of the data corresponding to different read threshold to calibrate the LUT.
The detail calibration steps are shown diagram 400 of
Once a code-word is decoded correctly by 410, statistics collector 251 or 450 will compare the correct code-word with each copy of the raw code-word and find out all of the bit flip count. It includes 0 to 1 count (z2o), which is the occurrences of 0 in decoded code-word and 1 in raw code-word in the same bit location; and 1 to 0 count (o2z), which is the occurrences of 1 in decoded code-word and 0 in raw code-word in the same bit location.
As shown in diagram 500 of
Hence LLR(x)=C*log2(delta(z2o(x))/delta(o2z(x)));
At the boundary of threshold, the total bit number of “0” or “1” should be used when calculating the difference. Meanwhile the LLR for different number of reads should have different boundary threshold.
For the case of up-page read of MLC and TLC as well as middle page read of TLC, the o2z and z2o will represent the combined flip count at two or three internal voltage thresholds. For example, the o2z and z2o for up-page of MLC in 600 (see
The last step of the calibration is to calculate the LLR value for each possible region with different voltage threshold. 700 (
With the multiple-LUT NAND flash channel calibration capability, it makes feasible to enable the adaptive multiple-RD. As such it can minimize the number of multiple reads once the M-RD is required. Hence it can reduce SSD latency once the M-RD happens.
Feasibility/Proof of Concept/Results Demonstration
An embodiment of the invention is the enabler for the adaptive multiple-read decoding, which has been proven to be effective to reduce the M-RD latency in case M-RD is needed. It is much more effective than the RAID recovery approach in case single read is not able to decode a code-word.
The adaptive multiple-read feature can be observed via monitoring the flash channel data traffic. If the same NAND flash page is read out after the threshold voltage adjustment by variable number times within a program and erase interval, then most likely adaptive multiple-read feature is implemented. Once adaptive multiple-read feature is identified, similar approach as embodiments of the present invention disclosure will be there either in hardware or firmware/software.
It will be understood that, although the terms “first”, “second”, “third”, etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the inventive concept.
Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the terms “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. As used herein, the term “major component” means a component constituting at least half, by weight, of a composition, and the term “major portion”, when applied to a plurality of items, means at least half of the items.
As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Further, the use of “may” when describing embodiments of the inventive concept refers to “one or more embodiments of the present invention”. Also, the term “exemplary” is intended to refer to an example or illustration. As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.
It will be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another element or layer, it may be directly on, connected to, coupled to, or adjacent to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, “directly coupled to”, or “immediately adjacent to” another element or layer, there are no intervening elements or layers present.
Any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of “1.0 to 10.0” is intended to include all subranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0, that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein.
Although exemplary embodiments of a method of flash channel calibration with multiple LUTs for adaptive multiple-read have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Accordingly, it is to be understood that a Disclosure—Method of Flash Channel Calibration with Multiple LUTs for Adaptive Multiple-Read constructed according to principles of this invention may be embodied other than as specifically described herein. The invention is also defined in the following claims, and equivalents thereof.
The present application claims priority to and the benefit of U.S. Provisional Application No. 62/027,683, filed Jul. 22, 2014, entitled “METHOD OF FLASH CHANNEL CALIBRATION WITH MULTIPLE LUTS FOR ADAPTIVE MULTIPLE-READ”, the entire content of which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62027683 | Jul 2014 | US |
