Patent Application
20210193671
The present invention relates to a non-volatile flash memory cell which has a select gate, a floating gate, a control gate, and an erase gate.
Split gate non-volatile flash memory cells having a select gate, a floating gate, a control gate and an erase gate are well known in the art. See for example U.S. Pat. Nos. 6,747,310 and 7,868,375. It is also known to form logic devices (i.e., low voltage and/or high voltage logic devices) on the same silicon chip, and in doing so sharing some of the processing steps for forming portions of both the memory and logic devices (e.g. forming gates for both memory cells and logic devices using the same polysilicon deposition process). However, other processing steps in forming the memory cells can adversely affect the previously fabricated logic devices, and vice versa, so it often can be difficult and complex to form both types of devices on the same wafer.
To solve problems with reduced channel widths by shrinking lithography size, FinFET types of structures have been proposed for memory cell structures. In a FinFET type of structure, a fin shaped member of semiconductor material connects the source to the drain regions. The fin shaped member has a top surface and two side surfaces. Current from the source to the drain regions can then flow along the top surface as well as the two side surfaces of the fin shaped member. Thus, the effective width of the channel region is increased, thereby increasing the current flow. However, the effective width of the channel region is increased without sacrificing more semiconductor real estate by “folding” the channel region into two side surfaces, thereby reducing the “footprint” of the channel region. Non-volatile memory cells using such FinFETs have been disclosed. Some examples of prior art FinFET non-volatile memory structures include U.S. Pat. Nos. 7,423,310, 7,410,913 and 8,461,640, the entire contents of each of which is incorporated herein by reference. What these prior art references do not contemplate is a FinFET type configuration for logic devices formed on the same wafer substrate as both non-volatile memory cells and high voltage transistor devices, both of a non-FinFET type configuration.
U.S. Pat. Nos. 9,972,630 and 10,249,631, the entire contents of each of which is incorporated herein by reference, disclose a memory device with FinFET type logic devices and non-FinFET memory cells. However, these patents fail to contemplate the contemporaneous formation of high voltage transistor devices of a non-FinFET type configuration.
The aforementioned problems and needs are addressed by a method of forming a device that comprises:
providing a silicon substrate with an upper surface and having first, second and third areas;
recessing the upper surface in the first and third areas of the substrate, but not in the second area of the substrate;
removing portions of the silicon substrate in the third area of the substrate to form an upwardly extending silicon fin having a pair of side surfaces extending up and terminating at a top surface;
performing a first implantation to form a first source region in the first area of the substrate;
performing a second implantation to form a first drain region in the first area of the substrate and to form a second source region and a second drain region in the third area of the substrate, wherein the first source region and the first drain region define a first channel region of the substrate extending there between, and wherein the second source region and the second drain region define a second channel region of the substrate extending there between;
performing a third implantation to form a third source region and a third drain region in the silicon fin to define a third channel region of the substrate extending there between along the top surface and the pair of side surfaces;
forming a floating gate disposed over and insulated from a first portion of the first channel region using a first polysilicon deposition;
forming a control gate disposed over and insulated from the floating gate using a second polysilicon deposition;
forming an erase gate disposed over and insulated from the first source region and a device gate disposed over and insulated from the second channel region using a third polysilicon deposition;
forming a word line gate disposed over and insulated from a second portion of the first channel region and a logic gate disposed over and insulated from the third channel region using a first metal deposition.
A device includes a silicon substrate having an upper surface, wherein the upper surface is planar in a first area and a third area of the substrate, the upper surface includes an upwardly extending silicon fin in a second area of the substrate, the silicon fin includes a pair of side surfaces extending up and terminating at a top surface, and the upper surface of the first and third areas is recessed below the top surface of the fin. A memory cell is disposed in the first area, a high voltage device is disposed in the third area, and a logic device is disposed in the second area. The memory cell includes spaced apart first source and first drain regions formed in the first area of substrate with a first channel region of the substrate extending there between, a floating gate of polysilicon disposed over and insulated from a first portion of the first channel region, a word line gate of metal disposed over and insulated from a second portion of the first channel region, a control gate of polysilicon disposed over and insulated from the floating gate, and an erase gate of polysilicon disposed over and insulated from the first source region. The high voltage device includes spaced apart second source and second drain regions formed in the third area of the substrate with a second channel region of the substrate extending there between, and a polysilicon gate disposed over and insulated from the second channel region. The logic device includes spaced apart third source and third drain regions formed in the silicon fin with a third channel region of the substrate extending there between along the top surface and the pair of side surfaces of the silicon fin, and a logic gate of metal disposed over and insulated from the third channel region.
Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.
Referring to
Nitride and oxide layers 14/12 are removed from the logic device area 4 (e.g. by one or more etches), leaving the surface of the substrate 10 exposed. The upper surface of the substrate 10 at this stage is stepped, where the portions of the upper surface of the substrate 10 in the memory cell and HV device areas 2/6 are recessed (i.e., lower) relative to the portion of the upper surface of the substrate 10 in the logic device area 4. An oxide layer 16 is then formed on the surface of the substrate 10 in all three areas 2/4/6, followed by the formation of a polysilicon (also referred to as poly) layer 18 by poly deposition on oxide layer 16. A chemical mechanical polish is then performed to remove the poly layer 18 from the logic device area 4, while maintaining the poly layer 18 in the memory cell and HV device areas 2/6, as illustrated in
An oxide layer 20 is formed on the poly layer 18, and a nitride layer 22 is formed on the oxide layer 20. An insulation layer (e.g., amorphous carbon) 24 is formed on nitride layer 22. The carbon layer 24 is patterned by forming photoresist, selectively removing strips of the photoresist in the logic device area 4, and removing the underlying exposed portions of the carbon layer 24 to form trenches 26 in the carbon layer 24 in the logic device area 4 that extend down to and expose the underlying nitride layer 22. Oxide spacers 28 are then formed in the trenches 26. Formation of spacers is well known in the art, and involves the deposition of a material over the contour of a structure, followed by an anisotropic etch process, whereby the material is removed from horizontal surfaces of the structure, while the material remains largely intact on vertically oriented surfaces of the structure (often with a rounded upper surface). In the present case, oxide spacers 28 are formed along the sidewalls of trenches 26, as shown in
Portions of the oxide spacers 28 in trenches 26 are removed by covering the structure with photoresist followed by partial photoresist removal so that portions of the oxide spacers are 28 are exposed. The exposed portions of the spacers 28 are then removed by oxide etch, leaving segments of the spacers 28 in trenches 26. After photoresist removal, the remaining portions of carbon layer 24 are removed by an etch. Next, the structure is covered with photoresist, which is exposed and developed to remove the photoresist from the logic device area 4, and leave parallel trench openings 23 in the memory cell area 2 and select areas in HV device area 6 that expose portions of the underlying nitride layer 22. A nitride etch is then used to remove the exposed portions of nitride layer 22, followed by an oxide etch to remove exposed portions of oxide layer 16 in the logic device area 4 and exposed portions of oxide layer 20 in memory/HV areas 2 and 6. The resulting structure is shown in
A silicon etch is then used to recess the exposed surface of the substrate 10 in the logic device area 4, forming fins 10a of the silicon substrate. Photoresist is formed and partially removed except for the logic device area 4. A poly etch removes exposed portions of poly layer 18, an oxide etch removes exposed portions of oxide layer 16, and a silicon etch removes exposed portions of the substrate 10, in the memory cell and HV device areas 2/6. The resulting structure is shown in
Photoresist is formed over the structure, and partially removed to expose the HV device area 6 and portions of the memory cell area 2, leaving portions of the nitride layer 36 exposed. A nitride etch is used to remove the exposed portions of nitride layer 36, exposing portions of poly layer 34. A poly etch is used to remove the exposed portions of poly layer 34, exposing portions of the ONO layer 32. An etch is used to remove the exposed portions of ONO layer 32, exposing portions of the poly layer 18. Oxide spacers 38 are then formed by oxide deposition and anisotropic etch. A poly etch is then used to remove the exposed portions of poly layer 18. The resulting structure is shown in
Photoresist is formed over the structure, and partially removed to expose portions of the memory cell area 2 (adjacent the ends of the poly layer strips 18). An implantation is then performed to form source regions 40 in the memory cell area 2 of the substrate underneath where the photoresist was removed. After photoresist removal, a layer of oxide (tunnel oxide) 42 is formed on the exposed ends of the poly layer strips 18 (e.g., by high temperature oxidation—HTO). A poly layer 44 is then formed over the structure by a third poly deposition. The poly layer 44 is planarized by CMP, and further etched with a poly etch back, leaving blocks of the poly layer 44 extending over the source regions 40 and along oxide layer 42 in the memory cell region 2, and leaving blocks of the poly layer 44 in the HV device area 6. After nitride hardmask 36 removal by a specific etch step, the structure is covered with a layer of oxide 46. The resulting structure is shown in
Photoresist is formed over the structure, and partially removed to expose portions of the oxide layer 46 in memory cell area 2 (i.e. portions over center portions of the poly strips 18). An oxide etch is used remove the exposed portions of oxide layer 46, exposing portions of poly layer 34. A poly etch is used to remove the exposed portions of poly layer 34, exposing portions of ONO layer 32. An ONO etch (i.e., oxide, nitride, oxide etches) is used to remove the exposed portions of ONO layer 32, exposing center portions of poly strips 18. A poly etch is used to remove the center portions of poly strips 18. The resulting structure is shown in
Photoresist 48 is formed over the structure, and partially removed to expose portions of the oxide layer 46 in logic device area 4. An oxide etch is used to remove the exposed portions of oxide layer 46, exposing portions of poly layer 34. A poly etch is used to remove poly layer 34 from the logic device area 4, exposing portions of ONO layer 32. An ONO etch is used to remove the exposed portions of ONO layer 32, exposing oxide 30. An oxide etch is used to recess oxide 30 below the tops of silicon fins 10a (i.e., so that silicon fins 10a protrude out from the recessed top surface of oxide layer 30), as shown in
One or more hard mask layers are then formed on the structure. For example, an amorphous carbon layer 52 is formed on the structure, and an oxide layer 54 is formed on amorphous carbon layer 52. Photoresist is formed on oxide layer 54, and partially removed to expose portions of the oxide layer 54 in the memory cell and logic device areas 2/4. An oxide etch is used remove the exposed portions of oxide layer 54, exposing portions of amorphous carbon layer 52. A carbon etch is used remove the exposed portions of amorphous carbon layer 52, exposing portions of dummy poly layer 50. A poly etch is used to remove exposed portions of dummy poly layer 50. This series of etches results in a trench 56 extending through dummy poly layer 50 in the memory cell area 2, and leaving a strip of dummy poly layer 50 extending over and between silicon fins 10a in the logic device area 4. After photoresist removal, photoresist is again formed on the structure, and partially removed to expose portions of the oxide layer 54 in the HV device area 6. An oxide etch is used remove the exposed portions of oxide layer 54, exposing portions of amorphous carbon layer 52. A carbon etch is used remove the exposed portions of amorphous carbon layer 52, exposing portions of oxide layer 46. An oxide etch is used to remove the exposed portions of oxide layer 46, exposing portions of poly layer 44. A poly etch is used to remove exposed portions of poly layer 44. This series of etches results in a block of the poly layer 44 remaining in the HV device area 6. The resulting structure is shown in
Nitride spacers 58 are formed on the exposed sidewalls of dummy poly layer 50 and poly layer 44 by nitride deposition and anisotropic etch. Photoresist 59 is formed on the structure, and partially removed to expose the oxide on the substrate surface adjacent blocks of dummy poly layer 50 (at the bottom of trench 56 of
Oxide layer 54 and amorphous carbon layer 52 are next removed by etch. A nitride layer 70 is formed on the structure, and a thick oxide layer 72 is formed on nitride layer 70. A CMP used to planarize oxide layer 72, using nitride layer 70 as a stop layer. Photoresist is formed over the structure, with those portions over strips of dummy poly layer 50 in the memory area 2 and logic device area 4 being selectively removed, exposing nitride layer 70. Etches are used to remove exposed portions of nitride layer 70, oxide layer 46, strips of dummy poly layer 50 and oxide layer 16, exposing the substrate 10 in the memory cell and logic device areas 2/4. After photoresist removal, an oxide layer 74 is formed on the structure, including on the exposed substrate 10. A layer of high K material 76 (i.e. having a dielectric constant K greater than that of oxide, such as HfO2, ZrO2, TiO2, Ta2O5, or other adequate materials) is formed on oxide layer 74. One or more metal layers are then formed on the structure. For example, a TiN layer 77 is formed on the structure, followed by a thick layer of tungsten 78, followed by CMP, leaving strips of metal 77/78 in the memory cell and logic device area 2/4 (effectively replacing dummy poly strips 50 previously removed), as shown in
While only two memory cells 100, four logic devices 102 and one HV device 104 are shown in
The above described memory device method and resulting structure provide many advantages, including the advantages of high operational performance and ease of manufacturing of planar memory cells 100 (i.e. memory cells that are formed on a planar region of the substrate) and planar HV devices 104 (i.e., devices that are formed on a planar region of the substrate) with the advantages of advanced combinations of embedded logic and memory devices where the logic devices 102 are condensed, non-planar logic devices (i.e., logic devices that are formed on and surrounding silicon fin structures). The FinFET transistor architecture of the logic devices 102 provides enhanced channel control with a tri-gate configuration and enables further scaling of the transistor dimensions.
Another advantage is that the upper surface of substrate 10 is recessed in the memory cell and HV device areas 2/6 relative to the logic device area. Specifically, the planar surfaces of the substrate 10 which constitute the channel regions in the memory cell and HV device areas 2/6 have a height that is recessed below the tops of the fins 10a in the logic device area 4 by a recess amount R as shown in
Still another advantage is the combination of polysilicon material for the HV gate 44b, floating gate 18a, control gate 34a and erase gate 44a (i.e., ease of manufacture, better control of tunneling between the floating and erase gates 18a/44a) and metal material insulated by a high K material for the word line gates 78a and logic gates 78b for enhanced conductivity and performance. Dummy poly layer 50 is used to form dummy gates in the memory cell and logic areas 2/4, which are removed and replaced with metal word line gates 78a for the memory cells and logic gates 78b for the logic devices.
A majority of the process fabrication for the memory cells and HV devices (including the formation of all the poly gates for the memory cells and HV devices) is performed before the formation of the logic gates, which reduces processing impacts on the CMOS baseline.
It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed, but rather in any order (unless there is an explicitly recited limitation on any order) that allows the proper formation of the memory cells and logic devices of the present invention. Lastly, single layers of material could be formed as multiple layers of such or similar materials, and vice versa.
It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed there between) and “indirectly on” (intermediate materials, elements or space disposed there between). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed there between) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements there between, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.
