Claims
- 1. In a method for forming plugs which comprises the steps of depositing an intermetal dielectric layer over a silicon substrate or a patterned metal layer; and forming vias of said intermetal dielectric layer; wherein the improvement comprises:
- a. forming a multiple layered barrier layer on said vias wherein said barrier layer consists of a TiN layer and a W layer and said barrier layer is formed by coating said vias with said TiN layer and depositing said W layer on said TiN layer; and then
- b. filling said vias with aluminum to form said plugs by depositing aluminum on said W layer, wherein said aluminum is deposited at a temperature above the melting point of aluminum.
- 2. The method of claim 1 wherein the material of the intermetal dielectric layer is selected from the group consisting of silicon dioxide, PSG, and BPSG.
- 3. The method of claim 1 wherein the material of the intermetal dielectric layer is selected from the group consisting of silicon dioxide, PSG, and BPSG; and said intermetal dielectric layer is deposited on a silicon substrate.
- 4. The method of claim 1 wherein the material of the intermetal dielectric layer is selected from the group consisting of silicon dioxide, PSG and BPSG; and the deposition of the intermetal dielectric layer is over a patterned metal layer.
- 5. The method of claim 1 wherein the deposited W has a thickness of about 500 angstroms and the deposited TiN has a thickness of about 100 angstroms.
Parent Case Info
This application is a Continuation of application Ser. No. 08/691,677, filed on Aug. 2, 1996, now abandoned.
US Referenced Citations (7)
Non-Patent Literature Citations (1)
Entry |
Silicon Processing for the VLSI Era, Volume 1--Process Technology, Wolf, S. and R.N. Tauber, Lattice Press, pp. 332 & 369, 1986. |
Continuations (1)
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Number |
Date |
Country |
Parent |
691677 |
Aug 1996 |
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