Claims
- 1. An integrated circuit device, comprising:
a semiconductor substrate; a first active feature in the semiconductor substrate of a first width; a second active feature in the semiconductor substrate having a second width substantially smaller than the first active feature; a first dummy-available region in the semiconductor substrate separating the first active feature from the second active feature by at least 20 microns, wherein the first dummy available-region is void of any active features; a first dummy feature in the first dummy-available region and in close proximity to the second active feature; and a second dummy-available region in the first dummy-available region separating the first dummy feature from the first active feature by at least 20 microns, wherein the second dummy-available region is void of dummy features.
- 2. The integrated circuit device of claim 1, wherein the second active feature and the first dummy feature are separated by a first distance.
- 3. The integrated circuit device of claim 2, further comprising:
a plurality of dummy features surrounding the second active feature and separated from the second active feature by the first distance.
- 4. The integrated circuit device of claim 3 further comprising a second dummy feature in the first dummy-available region and in close proximity to the first active feature.
- 5. The integrated circuit device of claim 1, wherein the first active feature comprises a plurality of high-density active features.
- 6. The integrated circuit device of claim 1, wherein the first dummy feature has a third width, the third width being at least as large as the second width.
- 7. The integrated circuit device of claim 6, wherein the third width is at least one micron.
- 8. The integrated circuit device of claim 7, wherein the first active feature comprises a plurality of high-density active features.
- 9. The integrated circuit device of claim 8 further comprising a second dummy feature in the first dummy-available region and in close proximity to the first active feature.
- 10. The integrated circuit device of claim 9, wherein the second active feature and the first dummy feature are separated by a first distance and further comprising:
a plurality of dummy features surrounding the second active feature and separated from the second active feature by the first distance.
- 11. The integrated circuit device of claim 1, wherein the second active feature comprises a plurality of high-density active features.
- 12. A method of making an integrated circuit device on a semiconductor substrate, comprising:
simultaneously forming in the semiconductor substrate a first active feature of a first width, a second active feature of a second width which is separated from the first active feature by a dummy-available region void of active features, and a first dummy feature of a third width in the dummy available region; and wherein the first dummy feature is in close proximity to the second active feature and separated from the first active feature by a dummy-free portion of the dummy-available region traversing a distance of at least five times the third width.
- 13. The method of claim 12 further comprising forming in the dummy available region a second dummy feature in close proximity to the first active feature.
- 14. The method of claim 13 wherein the third width is between approximately one to ten microns.
- 15. The method of claim 14 wherein the first active feature comprises a plurality of high-density active features.
- 16. An integrated circuit device formed on a semiconductor substrate, comprising:
a first region at a feature level having a first desirable dummy feature density of zero; a first local area in the first region; a second region at the feature level having a second desirable dummy feature density which is greater than the first desirable dummy feature density; a first active feature in the first local area; a second active feature in the first local area; a dummy-available region between the first active feature and the second active feature having a dummy-free region traversing a first distance; and a first dummy feature in a portion of the dummy-available region adjacent to the second active feature so that the first desirable dummy feature density is exceeded.
- 17. An integrated circuit device, comprising:
a first active feature region free from polishing dummy features; a polishing dummy feature region having a first polishing dummy feature density adjacent to and surrounding the first active feature region; and a dummy-available region adjacent to at least a portion of the polishing dummy feature region having a second polishing dummy feature density, wherein the second polishing dummy feature density is substantially less than the first polishing dummy feature density.
- 18. The integrated circuit device of claim 17, wherein the first active feature region is less than 400 square microns.
- 19. The integrated circuit device of claim 18, wherein the dummy-available region is at least 400 square microns.
- 20. The integrated circuit device of claim 19 being partially populated with active features.
- 21. The integrated circuit device of claim 20, wherein the polishing dummy feature region comprising at least rows of dummy features surrounding the first active feature region.
RELATED APPLICATION
[0001] This is related to U.S. patent application Ser. No. 09/340,697 filed Jun. 29, 1999, and entitled “Integrated Circuit Device And A Process For Designing A Mask” and is assigned to the current assignee hereof.