Patent Application
20240412974
The present invention relates to a method for forming a substance layer and a method for manufacturing a device by employing the same, and more specifically, to a method for forming an epitaxial semiconductor layer and a method for manufacturing a semiconductor device by employing the same.
As information and communication technology is advancing and demand for portable digital application devices such as smartphones, digital cameras, and tablet PCs is increasing, the semiconductor market is rapidly expanding. Semiconductor technology has secured growth momentum in the semiconductor market through scaling down integrated circuits over the past several decades. However, it is becoming increasingly difficult to secure technological competitiveness solely through technology which increases density or capacity through scaling down. Accordingly, research has recently been conducted to simultaneously improve device integration and to optimize performance through the development of substances and new manufacturing methods for three-dimensional device shape or high performance.
Meanwhile, various semiconductor substances are used in the manufacture of semiconductor devices, and depending on the composition and crystal structure of the substances, the performance or characteristics of the device may vary significantly. Furthermore, the characteristics of the device may be greatly influenced by the matching relationship or bonding characteristics between one substance layer and another substance layer adjacent to it. In particular, improvements in semiconductor substances having a single crystalline structure and the bonding interface formed thereby may be advantageous in securing excellent performance. However, the existing methods for growing single crystal semiconductors include a high-temperature vapor deposition method under the specific conditions or a method using molecular beams in a vacuum, which require high-temperature processes which place a thermal burden on the underlying layer or has limitations requiring a vacuum process.
Therefore, a manufacturing technology which may easily form a substance film with a single crystalline structure having excellent properties under various conditions and environments is desirable. In particular, this manufacturing technology may be advantageous for improving device performance and improving economic efficiency of manufacturing.
The technological object to be achieved by the present invention is to provide a method for forming an epitaxial semiconductor layer which may easily form a single crystalline semiconductor layer having excellent properties under various conditions and situations without heating the substrate to a high temperature or using a vacuum state.
In addition, the technological object to be achieved by the present invention is to provide a method for manufacturing a semiconductor device having excellent performance by applying the above-described method for forming an epitaxial semiconductor layer.
The objects to be solved by the present invention are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the description below.
According to embodiments of the present invention for achieving the above objects, there is provided a method for forming an epitaxial semiconductor layer comprising: a step for providing a crystallization base member having a single crystal structure; a step for forming a semiconductor layer having one of an amorphous structure and a polycrystalline structure in contact with the crystallization base member; a step for forming a heating layer which may be heated by a laser on the semiconductor layer; a step for melting the semiconductor layer by heating the heating layer by irradiating a laser to the heating layer; and a step for forming a single crystallized epitaxial semiconductor layer from the semiconductor layer through single crystallization of the semiconductor layer according to the single crystalline structure of the crystallization base member by cooling the molten semiconductor layer.
The crystallization base member may include any one of a single crystal silicon, a single crystal silicon germanium, and a single crystal germanium.
The semiconductor layer may include any one of a silicon, a silicon germanium, a germanium, a silicon carbide, GaAs, InGaAs, InAs, and InSb.
The heating layer may include at least one of metal and metal compounds.
The heating layer may include at least any one of TiN, Ti, TiSi, Ta, TaN, Co, CoSi, Ni, NiSi, Ru, W, WSi, Cu, Re, Mo, Nb, and Cr.
The heating layer may have a thickness of about 30 Å to 4,0000 Å.
The laser irradiated to the heating layer may have a wavelength of 0.02 μm to 11 μm.
In the step for melting the semiconductor layer, the laser irradiation time may be on the order of several ps to tens of μs.
The method may further include a step for forming a passivation layer on the heating layer.
The laser may be irradiated to the heating layer through the passivation layer.
The passivation layer may be an insulating layer containing an inorganic substance.
The crystallization base member may be a substrate member, a mask layer having at least one opening exposing a portion of the crystallization base member may be formed on the crystallization base member, and the semiconductor layer may be formed to fill the opening on the crystallization base member exposed by the opening.
The semiconductor layer may be formed to have the same thickness as the mask layer, or the semiconductor layer may be formed to have a thickness larger than the mask layer so as to cover the upper surface of the mask layer.
The crystallization base member may be disposed on an underlying layer, the crystallization base member may be formed to have a patterned layer structure having at least one opening exposing a portion of the underlying layer, and the semiconductor layer may be formed to fill the opening on the underlying layer exposed by the opening.
The semiconductor layer may be formed to have the same thickness as the crystallization base member, or the semiconductor layer may be formed to have a thickness larger than that of the crystallization base member to cover the upper surface of the crystallization base member.
According to another embodiment of the present invention, there is provided a method for manufacturing a semiconductor device comprising: a step for forming an epitaxial semiconductor layer using the method described above; and a step for forming a semiconductor device including the epitaxial semiconductor layer.
According to another embodiment of the present invention, there is provided a method for manufacturing a semiconductor device comprising: a step for providing a crystallization base member having a single crystal structure; a step for forming a mask layer on the crystallization base member having at least one opening exposing a portion of the crystallization base member; a step for forming a semiconductor layer having any one of an amorphous structure and a polycrystalline structure to fill the opening on the crystallization base member exposed by the opening; a step for forming a heating layer which may be heated by a laser on the semiconductor layer; a step for melting the semiconductor layer by heating the heating layer by irradiating a laser to the heating layer; a step for forming a single crystallized epitaxial semiconductor layer from the semiconductor layer through single crystallization of the semiconductor layer according to the single crystalline structure of the crystallization base member by cooling the molten semiconductor layer; and a step for forming a semiconductor device including the epitaxial semiconductor layer.
The semiconductor layer may be formed to have the same thickness as the mask layer, or the semiconductor layer may be formed to have a thickness larger than the mask layer so as to cover the upper surface of the mask layer.
The crystallization base member may include any one of a single crystal silicon, a single crystal silicon germanium, and a single crystal germanium.
The semiconductor layer may include any one of a silicon, a silicon germanium, a germanium, a silicon carbide, GaAs, InGaAs, InAs, and InSb.
The heating layer may include at least one of a metal and metal compounds.
The semiconductor device may include a transistor including the epitaxial semiconductor layer as an active layer.
According to another embodiment of the present invention, there is provided a method for manufacturing a semiconductor device comprising: a step for preparing a substrate structure in which a crystallization base member having a single crystalline structure is formed on an underlying layer, wherein the crystallization base member is formed in a patterned layer structure having at least one opening exposing a portion of the underlying layer; a step for forming a semiconductor layer having any one of an amorphous structure and a polycrystalline structure to fill the opening on the underlying layer exposed by the opening; a step for forming a heating layer which may be heated by a laser on the semiconductor layer; a step for melting the semiconductor layer by heating the heating layer by irradiating a laser to the heating layer; a step for forming a single crystallized epitaxial semiconductor layer from the semiconductor layer through single crystallization of the semiconductor layer according to the single crystalline structure of the crystallization base member by cooling the molten semiconductor layer; and a step for forming a semiconductor device including the epitaxial semiconductor layer.
The semiconductor layer may be formed to have the same thickness as the crystallization base member, or the semiconductor layer may be formed to have a thickness larger than that of the crystallization base member to cover the upper surface of the crystallization base member.
The crystallization base member may include any one of a single crystal silicon, a single crystal silicon germanium, and a single crystal germanium.
The semiconductor layer may include any one of a silicon, a silicon germanium, a germanium, a silicon carbide, GaAs, InGaAs, InAs, and InSb.
The heating layer may include at least one of a metal and metal compounds.
The semiconductor device may include a transistor including the epitaxial semiconductor layer as an active layer.
According to embodiments of the present invention, it is possible to implement a method for forming an epitaxial semiconductor layer which may easily form a semiconductor layer with a single crystalline structure having excellent characteristics under various conditions and situations without heating the substrate to a high temperature or using a vacuum state. In particular, an epitaxial semiconductor layer may be more easily formed in a completely different way from vapor deposition by using the melting and temperature profile of the semiconductor layer according to the indirect heating method using a laser.
A semiconductor device having excellent performance may be easily manufactured by applying the method for forming an epitaxial semiconductor layer according to the embodiments.
Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiments of the present invention to be described below are provided to more clearly explain the present invention to those skilled in the art, and the scope of the present invention is not limited by the following embodiments, and the embodiments may be modified in many different forms.
The terms used in this specification are used to describe specific embodiments and are not intended to limit the present invention. The terms indicating a singular form used herein may include plural forms unless the context clearly indicates otherwise. Also, as used herein, the terms, “comprise” and/or “comprising” specify the presence of the stated shape, step, number, operation, member, element, and/or group thereof and does not exclude the presence or addition of one or more other shapes, steps, numbers, operations, elements, elements and/or groups thereof. In addition, the term, “connection” used in this specification means not only a direct connection of certain members, but also a concept including an indirect connection in which other members are interposed between the members.
In addition, in the present specification, when a member is said to be located “on” another member, this arrangement includes not only a case in which a member is in contact with another member, but also a case where another member exists between the two members. As used herein, the term, “and/or” includes any one and all combinations of one or more of the listed items. In addition, the terms of degree such as “about” and “substantially” used in the present specification are used as a range of values or degrees, or as a meaning close thereto, taking into account inherent manufacturing and substance tolerances, and exact or absolute figures provided to aid in the understanding of this application are used to prevent the infringers from unfairly exploiting the stated disclosure.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. A size or a thickness of areas or parts shown in the accompanying drawings may be slightly exaggerated for clarity of the specification and convenience of description. The same reference numbers indicate the same configuring elements throughout the detailed description.
Referring to
Next, the semiconductor layer 20 contacting with the crystallization base member 10, and having either an amorphous structure or a polycrystalline structure may be formed. The semiconductor layer 20 may include, for example, a group IV-based semiconductor such as a silicon Si, a silicon germanium SiGe, a germanium Ge, and a silicon carbide SiC, or may include group II-VI or group III-V semiconductors such as GaAs, InGaAs, InAs, and InSb. The thickness of the semiconductor layer 20 may be, for example, about 10 Å to 2,000 Å, but the embodiments of the present disclosure are not limited thereto.
A heating layer 30 which may be heated by a laser may be formed on the semiconductor layer 20. The heating layer 30 may include at least any one of a metal and metal compounds. For example, the heating layer 30 may include at least any one of TiN, Ti, TiSi, Ta, TaN, Co, CoSi, Ni, NiSi, Ru, W, WSi, Cu, Re, Mo, Nb, and Cr. It may be desirable for the heating layer 30 to have a thickness of about 30 Å to 4,000 Å to improve its function, but the present embodiment is not limited thereto, and the appropriate thickness of the heating layer 30 may vary depending on the cases. The heating layer 30 may have a high absorption rate for the laser and may serve to heat and melt the semiconductor layer 20 by absorbing the laser, and may also serve as a capping layer which traps the heat transferred to the semiconductor layer 20 or radiated from the heated semiconductor layer 20 toward the semiconductor layer 20. In this regard, the heating layer 30 may be referred to as a ‘laser absorption layer (a high absorption layer)’, a ‘thermal capping layer’, or a ‘heat transfer layer’.
The heating layer 30 may serve to suppress side effects such as deformation of the surface of the semiconductor layer 20 or the occurrence of protrusions on the surface of the semiconductor layer 20 in the subsequent heating process by laser irradiation. As the heating layer 30 may have a higher melting point than the semiconductor layer 20, even if the semiconductor layer 20 melts in the subsequent process, the heating layer 30 does not melt and its structure (a layer structure) may be maintained.
Furthermore, a passivation layer 40 may be further formed on the heating layer 30. The passivation layer 40 may be an insulating layer containing an inorganic substance or an insulating layer based on an inorganic substance. For example, the passivation layer 40 may include at least any one of a silicon oxide (SiO2), a silicon nitride (SixNy), and silicon nitride (SiON). For example, the passivation layer 40 may have a thickness of approximately 10 Å to 500 Å. The passivation layer 40 may serve to prevent the heating layer 30 from deformation such as hilllock or pinholes on the surface of the heating layer 30 generated by thermal stress during laser irradiation. However, the formation of the passivation layer 40 is optional and the formation may be omitted.
Referring to
The laser L1 irradiated to the heating layer 30 may have a wavelength of approximately 0.02 μm to 11 μm. When at least one of these conditions is satisfied, the heating layer 30 may be more easily heated by using the laser L1, and the semiconductor layer 20 in contact with it may be melted more easily by heating the heating layer 30. Meanwhile, in the step for melting the semiconductor layer 20, the irradiation time of the laser L1 may be on the order of several ps to tens of microseconds. However, the range of the irradiation time is exemplary and may vary depending on the case.
In the embodiment of the present invention, as the heating layer 30 is heated by laser L1 irradiation, and the semiconductor layer 20 is melted by heating the heating layer 30, when the semiconductor layer 20 is melted, the crystallization base member 10 may not melt. Therefore, the crystallization process on the semiconductor layer 20 may be performed while maintaining the single crystalline structure of the crystallization base member 10 without a high temperature heating process. When the semiconductor layer 20 is melted according to the heating method using the laser L1, an appropriate temperature profile may be applied in the thickness direction from the crystallization base member 10 to the heating layer 30 by controlling the intensity of the irradiated laser L1. For example, when the semiconductor layer 20 is melted, the temperature of the upper part of the semiconductor layer 20 may be relatively high, and the temperature of the lower part of the semiconductor layer 20 may be relatively low. In other words, the temperature of the upper part of the molten semiconductor layer 20a may be relatively higher than the temperature of the lower part. Furthermore, the temperature of the heating layer 30 may be higher than the temperature of the semiconductor layer 20a. The temperature of the crystallization base member 10 may be lower than the temperature of the semiconductor layer 20a.
Referring to
Furthermore, the cooling process in
Referring to
As a result of comparing the results of
Referring to
Referring to
Referring to
Table 1 below summarizes the results confirming whether the heating layer was applied and whether the epitaxial semiconductor layer was formed according to the thickness of the heating layer (i.e., whether the epitaxial process was successful). The case where TIN was used as a heating layer and the case where no heating layer was used (i.e., No TiN) were evaluated, the cases where the thickness of the heating layer (i.e., TiN layer) was 100 Å and 500 Å were evaluated, and the cases where the laser powers were 60 W, 120 W, and 250 W, were evaluated. The process conditions, including the power of the laser, are exemplary and the embodiments of the present invention are not limited thereto. The power of the laser may also vary depending on the temperature of the object to be processed.
Referring to Table 1, the part written as Epitaxy indicates a case in which an epitaxial semiconductor layer is formed, and the blank space indicates a case in which an epitaxial semiconductor layer is not formed. If the laser power is too low, the epitaxial semiconductor layer may not be formed regardless of whether a heating layer is applied. In the case where a heating layer is not used (i.e., No TiN), it may be seen that even if the laser power is increased, the epitaxial semiconductor layer is not formed within the predetermined evaluated power range. It may be seen that when the thickness of the heating layer (i.e., TIN layer) is relatively thick, an epitaxial semiconductor layer may be easily formed at lower laser power compared to the case where the thickness of the heating layer (i.e., TiN layer) is relatively thin. This may be because the thicker the thickness of the heating layer is within a predetermined range, the easier it is to heat by laser absorption and the easier it is to control the cooling temperature profile. Therefore, when a heating layer of an appropriate thickness is used, an epitaxial semiconductor layer according to the embodiment may be formed more easily.
Referring to
Referring to
Referring to
The method for forming an epitaxial semiconductor layer according to embodiments of the present invention described above may be applied to the manufacturing methods of various semiconductor devices. For example, the method for forming an epitaxial semiconductor layer according to embodiments may be applied in place of existing gas phase epitaxy or molecular beam epitaxy, and in the situations or the conditions where it is difficult to apply existing gas phase epitaxy or molecular beam epitaxy, it may be usefully applied. A method for manufacturing a semiconductor device according to an embodiment of the present invention may include a step for forming an epitaxial semiconductor layer by a method according to the above-described embodiment and a step for forming a semiconductor device including the epitaxial semiconductor layer.
Referring to
Next, a mask layer 110 having at least one opening H10 exposing a portion of the crystallization base member 100, that is, a single crystal surface may be formed on the crystallization base member 100. The mask layer 110 may be formed by a predetermined insulating substance and may have a higher melting point than that of the semiconductor layer (120 in
Referring to
Next, a heating layer 130 which may be heated by a laser may be formed on the semiconductor layer 120. The substance of the heating layer 130 may correspond to the substance of the heating layer 30 of
In one embodiment, the heating layer 130 may continuously cover the semiconductor layer 120 in common across the semiconductor layer 120 having regions separated from each other by the mask layer 110. In another embodiment, the heating layer 130 may be formed selectively and discretely or discontinuously only on each region of the semiconductor layer 120 exposed by the mask layer 110.
Furthermore, a passivation layer 140 may be further formed on the heating layer 130. The passivation layer 140 may be an insulating layer containing an inorganic substance or an insulating layer based on an inorganic substance. For example, the passivation layer 140 may include at least one of silicon oxide SiO2, silicon nitride SixNy, and silicon nitride SiON. For example, the passivation layer 140 may have a thickness of about 50 Å to 500 Å. However, the formation of the passivation layer 140 is optional, and in some cases, it may not be formed.
Referring to
Next, the molten semiconductor layer 120a is cooled to single-crystallize the semiconductor layer 120a according to the single crystalline structure of the crystallization base member 100, thereby single crystallizing the semiconductor layer 120a. As a result, as shown in
Subsequently, a single crystalline structure as shown in
Next, a semiconductor device including the epitaxial semiconductor layer 120b may be formed. For example, as shown in
The transistor T10 may exhibit excellent operating characteristics depending on the substance composition or crystallization state of the epitaxial semiconductor layer 120b. For example, when the epitaxial semiconductor layer 120b has a single crystalline structure and is a strained substance layer, the transistor T10 may exhibit excellent operating characteristics. If the substance of the epitaxial semiconductor layer 120b and the substance of the crystallization base member 100 are different from each other, strain may occur in the epitaxial semiconductor layer 120b during the crystallization (single crystallization) process of the epitaxial semiconductor layer 120b due to the difference in lattice constant between them.
In the step of
Referring to
Referring to
Next, the molten semiconductor layer 125a is cooled to single-crystallize the semiconductor layer 125a according to the single crystalline structure of the crystallization base member 100, thereby single crystallizing the semiconductor layer 125a. As a result, as shown in
Subsequently, after removing the passivation layer 140 and the heating layer 130, a structure as shown in
Thereafter, although not shown, a semiconductor device including an epitaxial semiconductor layer 125b′ may be formed. For example, a transistor structure as shown in
Referring to
The substance of the crystallization base member 210 may correspond to the crystallization base member 10 of
Referring to
In this embodiment, the substance of the semiconductor layer 220 may be a different substance from the substance of the crystallization base member 210. The substance of the semiconductor layer 220 may be a substance with a lower melting point than that of the substance of the crystallization base member 210. For example, when the crystallization base member 210 is silicon Si, the semiconductor layer 220 may be silicon germanium SiGe or germanium Ge. However, the combination of the substance of the crystallization base member 210 and the substance of the semiconductor layer 220 may vary in various ways.
Next, a heating layer 230 which may be heated by a laser may be formed on the semiconductor layer 220. The heating layer 230 may be formed on the semiconductor layer 220 and the crystallization base member 210. The substance of the heating layer 230 may correspond to the substance of the heating layer 30 of
Furthermore, a passivation layer 240 may be further formed on the heating layer 230. The passivation layer 240 may be an insulating layer containing an inorganic substance or an insulating layer based on an inorganic substance. For example, the passivation layer 240 may include at least one of silicon oxide SiO2, silicon nitride SixNy, and silicon nitride SiON. For example, the passivation layer 240 may have a thickness of approximately 10 Å to 500 Å. However, the formation of the passivation layer 240 is optional, and in some cases, it may not be formed.
Referring to
Next, the molten semiconductor layer 220a is cooled to single-crystallize the semiconductor layer 220a according to the single crystalline structure of the side surface of the crystallization base member 210, thereby singly crystallizing the semiconductor layer 220a along the horizontal direction. As a result, as shown in
Optionally, in a subsequent process, a structure as shown in
Next, a semiconductor device including the epitaxial semiconductor layer 220b may be formed. For example, as shown in
The transistor T20 may exhibit excellent operating characteristics depending on the substance composition or crystallization state of the epitaxial semiconductor layer 220b. For example, when the epitaxial semiconductor layer 220b has a single crystalline structure and is a strained substance layer, the transistor T20 may exhibit excellent operating characteristics. If the substance of the epitaxial semiconductor layer 220b and the substance of the crystallization base member 210 are different from each other, strain may occur in the epitaxial semiconductor layer 220b during the crystallization (single crystallization) process of the epitaxial semiconductor layer 220b due to the difference in lattice constant between them.
In the step of
Referring to
Referring to
Next, the molten semiconductor layer 225a is cooled to single-crystallize the semiconductor layer 225a according to the single crystalline structure of the crystallization base member 210, thereby single crystallizing the semiconductor layer 225a. As a result, as shown in
Subsequently, after removing the passivation layer 240 and the heating layer 230, a structure as shown in
Thereafter, although not shown, a semiconductor device including an epitaxial semiconductor layer 225b′ may be formed. For example, a transistor structure as shown in
In the step of
Referring to
As shown in
The method for manufacturing a semiconductor device according to the embodiments specifically described with reference to
As described above, according to embodiments of the present invention, it is possible to implement a method for forming an epitaxial semiconductor layer which may easily form a semiconductor layer of a single crystalline structure having excellent properties under various conditions and situations may be easily formed without heating the substrate to a high temperature or using a vacuum state. In particular, an epitaxial semiconductor layer may be more easily formed in a completely different way from vapor deposition by using the melting and temperature profile of the semiconductor layer according to the indirect heating method using a laser. If the method for forming an epitaxial semiconductor layer according to the above-described embodiments is applied, a semiconductor device having excellent performance may be easily manufactured.
In this specification, the preferred embodiments of the present invention have been disclosed, and although specific terms have been used, they are only used in a general sense to easily explain the technological content of the present invention and to help understanding the present invention, and they are not used to limit the scope of the present invention. It is obvious to those having ordinary skill in the related art to which the present invention belong that other modifications based on the technological idea of the present invention may be implemented in addition to the embodiments disclosed herein. It will be understood to those having ordinary skill in the related art that in connection with a method for forming an epitaxial semiconductor layer according to the embodiments described with reference to
The embodiments of the present invention may be applied to the manufacture of epitaxial semiconductor layers and semiconductor devices including the same. The method for forming an epitaxial semiconductor layer according to embodiments may be applied to a manufacture process of various devices such as transistors, memory devices, diodes, optical devices, and power devices.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2021-0119365 | Sep 2021 | KR | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/KR2022/013088 | 9/1/2022 | WO |
