Method of forming semiconductor device structures using hardmasks

Abstract

A first hardmask layer is provided over a substrate, and a second hardmask layer is provided over the first hardmask layer. The second hardmask layer is patterned to form a second hardmask structure having sidewalls. A sacrificial layer of a sacrificial material is conformally deposited such that the deposited sacrificial layer has substantially horizontal and vertical portions. The horizontal portions of the sacrificial layer are removed to form lines of the sacrificial material adjacent to the sidewalls of the second hardmask lines. The sacrificial layer is at least partially removed to structure the sacrificial material and the remaining sacrificial layer is used to structure the first hardmask. The second hardmask structures is removed to uncover portions of the first hardmask. Uncovered portions of the substrate are etched, thereby forming structures in the substrate below the first hardmask.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a cross-sectional view of an NROM cell.

FIG. 1B shows a plan view of a memory device comprising NROM cells.

FIG. 2 shows a cross-sectional view of a substrate after patterning a photoresist layer.

FIG. 3 shows a cross-sectional view of the substrate after patterning a hardmask layer.

FIG. 4 shows a cross-sectional view of the substrate after thinning the hardmask lines.

FIG. 5 shows a cross-sectional view of the substrate after depositing a sacrificial layer.

FIG. 6A shows a cross-sectional view of the substrate after patterning a photoresist layer.

FIG. 6B shows a plan view of the substrate after patterning the photoresist layer.

FIG. 7A shows a cross-sectional view of the substrate after performing an etching step.

FIG. 7B shows a plan view of the substrate after performing the etching step.

FIG. 8A shows a cross-sectional view of the substrate after removing the hardmask material.

FIG. 8B shows a plan view of the substrate after removing the hardmask material.

FIG. 9A shows a cross-sectional view of the substrate after patterning a photoresist layer.

FIG. 9B shows a plan view of the substrate after patterning the photoresist layer.

FIG. 10A shows a cross-sectional view of the substrate after performing an etching step.

FIG. 10B shows a plan view of the substrate after performing the etching step.

FIG. 11 shows a cross-sectional view of the substrate after performing a further etching step.

FIG. 12A shows a cross-sectional view of the memory device according to the present invention.

FIG. 12B shows a plan view of a memory device according to the present invention.

FIG. 13 shows a plan view of a memory device according to another embodiment of the present invention.

FIG. 14 shows a plan view of an array of conductive lines according to an embodiment of the present invention.

FIG. 15 shows for a different embodiment of the present invention a plan view (i.e. a top view) of a part of a structure to be manufactured having a random pattern.

FIG. 16 shows a cross section through a layered stack with a first hardmask and a second hardmask and a structured photoresist layer.

FIG. 17 shows a cross section through the layered stack after the pattering of the second hardmask.

FIG. 18 shows a cross section through the layered stack after the conformal depositing of a sacrificial layer on the second hardmask.

FIG. 19 shows a cross section after the horizontal parts of the sacrificial layer has been removed.

FIG. 19A shows a top view of the second hardmask, the rims of the hardmask lined with sacrificial material.

FIG. 20 shows a cross section of the layered stack with the second hardmask removed.

FIG. 20A shows a top view of the remaining parts of the sacrificial layer after removal of the second hardmask.

FIG. 21 shows a cross section of the layered stack with a further photoresist layer to pattern the structure made of sacrificial material.

FIG. 21A shows a top view of the partially by photoresist covered structure made of sacrificial material.

FIG. 22 shows a cross section with the remaining parts of the sacrificial layer.

FIG. 22A shows a top view with the remaining parts of the sacrificial layer.

FIG. 23 shows a cross section with another patterned photoresist layer for the pattering below lying layers.

FIG. 23A shows a top view of the patterned photoresist layer.

FIG. 24 shows a cross section of the patterned first hardmask layer.

FIG. 24A shows a top view of the pattering first hardmask layer.

FIG. 25 shows a cross section of the patterned first hardmask layer.

Claims

1. A method for forming a structure of a semiconductor device, comprising: providing a layer stack comprising a first hardmask layer over a substrate and a second hardmask over the first hardmask;patterning the second hardmask layer to form a second hardmask structure having sidewalls;conformally depositing a sacrificial layer of a sacrificial material such that the deposited sacrificial layer has substantially horizontal and vertical portions;removing the horizontal portions of the sacrificial layer to form lines of the sacrificial material adjacent to the sidewalls of the second hardmask lines;at least partially removing the sacrificial layer for structuring the sacrificial material and using the remaining sacrificial layer for structuring the first hardmask;removing the second hardmask structures to uncover portions of the first hardmask; andetching the uncovered portions of the layer stack thereby forming structures in the substrate.

2. The method according to claim 1, wherein the lines of the sacrificial material are at least partially cut due to the at least partial removing of the sacrificial layer.

3. The method according to claim 1, wherein the second hardmask layer is removed before at least partially removing the sacrificial layer.

4. The method according to claim 1, wherein structures of the sacrificial layer and the first hardmask are at least partially covered with a photoresist layer and the first hardmask and the structures in the sacrificial layer are etched using the photoresist layer as a mask to form a pattern in the first hardmask layer.

5. The method according to claim 4, wherein the pattern is used to form at least one of landing pads, lines, and logic transistors.

6. The method according to claim 1, wherein the thickness of the sacrificial layer is between 10 and 60 nm

7. The method according to claim 6, wherein the thickness of the sacrificial layer is between 30 and 50 nm.

8. The method according to claim 1, wherein the sacrificial layer comprises a material which can be selectively etched against the material of the first hardmask and the second hardmask.

9. The method according to claim 8, wherein the sacrificial layer comprises a material from the group of SiO2 forms, BSG, silicon, polysilicon, and TEOS.

10. The method according to claim 1, wherein the first hardmask comprises a material from the group of Carbon, Si3N4, and polysilicon.

11. The method according to claim 1, wherein the second hardmask comprises a material from the group of SiO2, TEOS, and Si3N4.

12. The method according to claim 1, wherein structuring of the sacrificial layer and structuring of the first hardmask are repeated at least once.

13. The method according to claim 12, wherein a plurality of spacers comprising sacrificial material is used to form structures with varying thickness.

14. The method according to claim 13, wherein the spacers have different thicknesses.